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检索条件"机构=Department for Systems and Circuit Design"

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Modeling Communications in SoC and Co-simulation Analysis with IEEE 1666 SystemC 32

Modeling Communications in SoC and Co-simulation Analysis wi...

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32nd Telecommunications Forum, TELFOR 2024

作者： Shyam, Shilpa Paoli, Gerhard Scherr, Wolfgang Carinthia University of Applied Sciences Department of Integrated Systems and Circuit Design Villach Austria

ISBN: (纸本)9798350391053

IEEE 1666 (SystemC) plays a vital role in system level design and verification of complex communication circuits along with several other modeling languages. It is capable of providing a powerful framework for modeling and simulating System on Chip (SoC) architectures, helping designers to explore system-level behaviour and optimise performance early in the development process. This paper carries out two primary investigations - first, it examines the differences in computation time while modeling circuits both simple and complex with Simulink and SystemC TDF (Timed Data Flow). The results show that SystemC TDF outpaces Simulink in terms of speed irrespective of the circuit complexity. The second investigation is a comparative study to analyse the ability of Matlab and Octave for co-simulation with SystemC. Co-simulation allows the integration of components in several domains along with high flexibility in system verification. The co-simulation flow starts with a sinusoidal source generated in Matlab which is used as an input source for a SystemC TDF module whose output is further post-processed in Matlab. In addition, similar investigations are done with Octave, using it for both post and pre-processing. The computational time in both cases are evaluated for each stages of the co-simulation flow and proves that Matlab is significantly faster than Octave in the investigated setups. © 2024 IEEE.

关键词： MATLAB

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Optimization of a CCM Steady State Boost Converter Power Supply for a Biomedical Sensor

Optimization of a CCM Steady State Boost Converter Power Sup...

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2023 IEEE International Conference on Engineering Veracruz, ICEV 2023

作者： Cardenas-Ruvalcaba, Roberto B. Chavez-Hurtado, Jose L. Aguilera-Galicia, Cuauhtemoc R. Martinez-Guerrero, Esteban Iteso - the Jesuit University of Guadalajara Research Group on Integrated Circuit Design Department of Electronics Systems and Informatics Tlaquepaque Mexico

ISBN: (纸本)9798350312959

Applications of the boost converter are becoming more popular in portable biomedical systems because they need to increase the input voltage coming from a small LR 44 battery or other source. This work presents a procedure for optimizing a boost converter power supply for a biomedical sensor. The initial design is obtained by using a first-grade model to calculate the boost converter components, then an optimization procedure is applied based on the Nelder Mead algorithm, which is performed using a Matlab - LTspice driver. Values of the inductor and capacitor, as well as the boost converter's duty cycle and switching frequency are used as optimization variables. design specifications include the average and ripple input current, the average and ripple output voltage, and the output current and its ripple. Results show a trade-off between the output voltage and the input current of the boost converter topology presented. At the end of the optimization process, the best component values are selected based on the electrical parameters that meet the specifications. © 2023 IEEE.

关键词： Pulse width modulation

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A Two Stage Miller OpAmp with Low Voltage Cascode Current Source with High EMI Immunity

A Two Stage Miller OpAmp with Low Voltage Cascode Current So...

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2023 International Symposium on Electromagnetic Compatibility - EMC Europe, EMC Europe 2023

作者： Shivdeep Sharma, Sahil Boyapati, Subrahmanyam Das, Devarshi Mrinal Indian Institute of Technology Ropar Department of Electrical Engineering Rupnagar India Carinthia University of Applied Sciences Integrated Systems and Circuit Design Group Carinthia Austria

ISBN: (纸本)9798350324006

Electromagnetic Interference (EMI) at the input of an Operational Transconductance Amplifier (OTA) leads to a DC offset voltage at the output. The amount of EMI-induced offset depends on the frequency and amplitude of the interferer signal. Various phenomena are dominant at different frequencies, such as the asymmetric slew rate is responsible for offset induced at frequencies around the Unity Gain Frequency (UGF). This paper identifies the causes and presents a design approach to optimize the slew rate and reduce the output offset without using overhead area and power. Channel length modulation of the tail current source transistor and its reduced impedance is due to the effective capacitance (CT) at the tail node becoming the culprit and adding more asymmetry to the slew rate. This is addressed using the cascode tail current source and additional gate-to-source capacitance Cgsx. Two-stage Miller OTA is designed in the standard 0.18 μm CMOS technology. Monte Carlo and the post-layout simulation results are presented to consider the parasitics, process variations, and mismatch effects. © 2023 IEEE.

关键词： Operational amplifiers

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Modeling Communications in SoC and Co-simulation Analysis with IEEE 1666 SystemC

Modeling Communications in SoC and Co-simulation Analysis wi...

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Telecommunications Forum (TELFOR)

作者： Shilpa Shyam Gerhard Paoli Wolfgang Scherr Department of Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria

ISBN: (数字)9798350391060

ISBN: (纸本)9798350391077

关键词： Analytical models Software packages System verification Computational modeling circuits Telecommunications System-on-chip MATLAB Integrated circuit modeling System-level design

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design Automation of a 2GHz Dynamic Comparator Using the CCC Framework

Design Automation of a 2GHz Dynamic Comparator Using the CCC...

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Austrian Workshop on Microelectronics (Austrochip)

作者： Rajani Arasada Violeta Petrescu Wolfgang Scherr Gerhard Paoli Santiago Martin Sondon Johannes Sturm Department of Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria

ISBN: (数字)9798331516178

ISBN: (纸本)9798331516185

circuit design automation is of great importance for modern electronics, enabling rapid prototyping and optimisation of analog circuits. This work exemplifies the application of the CUAS Cell Creator (CCC) framework based on Python language along with the $g_{m}/I_{D}s$ method and precomputed look-up tables for automating the design of analog circuits with a specific focus on high speed dynamic comparators. To achieve the highly demanding specifications in terms of comparator speed and offset many design iterations are necessary, in which every step is traditionally done manually by the analog designer modifying the MOS transistor sizing, until the desired performance is achieved. Describing the circuit functionality using the classical Kirchoff equations together with unified treatment of all the regions of operation of the MOS transistor using $g_{m}/I_{D}$ method, provides an efficient way for design automation and reuse.

关键词： MOSFET design automation Automation Conferences Analog circuits Rapid prototyping Table lookup Microelectronics circuit synthesis Optimization

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An Easy to Use Python Framework for circuit Sizing from designers for designers

An Easy to Use Python Framework for Circuit Sizing from Desi...

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Austrian Workshop on Microelectronics (Austrochip)

作者： Wolfgang Scherr Violeta Petrescu Johannes Sturm Dirk Hammerschmidt Santiago Sondon Department of Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria

ISBN: (数字)9798331516178

ISBN: (纸本)9798331516185

circuit sizing of analogue building blocks is often still done by hand. Experts in circuit design are not necessarily experts in computer science and programming. Thus, it is not easy to find scripts providing automated sizing procedures. In this work, a Python framework is presented, simplifying the use of analogue design automation. It provides a tool- and technology agnostic approach and is explicitly developed with focus on circuit design. Therefore, the entry barrier is kept as low as possible. The framework supports an “agile” approach for developing new ideas interactively as well as a “waterfall” mode to simplify sequential design tasks. But describing e.g. iterations in a script, as designers do in their sizing process manually, makes re-use possible. With very little extra effort, re-use for multiple MOS technologies can be enabled as well. The idea is not to replace design engineers, but to increase design efficiency and improve re-use within and across technologies and design communities, by simple to read and use executable notebooks. Later, such notebooks can be collected in asset classes. This is demonstrated using simple examples.

关键词： design automation Conferences Programming circuit synthesis Microelectronics Python

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A Self-Calibration Logic circuit Agnostic to Offset Calibration Technique for High-Precision Dynamic Comparator 4

A Self-Calibration Logic Circuit Agnostic to Offset Calibrat...

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4th IEEE Women in Technology Conference, WINTECHCON 2023

作者： Sharma, Nidhi Srivastava, Rajesh K. Hande, Vinayak Sehgal, Deep Das, Devarshi Mrinal Indian Institute of Technology Ropar Department of Electrical Engineering Rupnagar India Semi-conductor Laboratory S.A.S Nagar India Carinthia University of Applied Sciences Integrated Systems and Circuit Design Villach Austria

ISBN: (纸本)9798350300567

This paper proposes a calibration technique agnostic calibration logic circuitry for the self-calibration of the high-precision dynamic comparator, which can be used in major self-calibration techniques to activate the calibration and offset polarity change detection for completion of the calibration. This paper also briefly reviews the different comparator offset cancellation techniques, i.e., auto-zeroing, self-calibration, and chopper stabilization. The proposed calibration logic is implemented in a dynamic comparator's effective trans-conductance controlled offset calibration in SCL 180 nm technology. The standard deviation of the input-referred offset of the comparator is reduced to 445 μV from 2.85 mV with a complete calibration range of 5σ offset, therefore qualifying it for high-speed flash ADCs and asynchronous SAR ADCs. The power consumption at 1 GHz operating frequency is 154.6 μW. © 2023 IEEE.

关键词： Calibration

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Comparative Analysis of Modeling Communication in SoCs for the Shift-Left Paradigm using IEEE 1666 SystemC 32

Comparative Analysis of Modeling Communication in SoCs for t...

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32nd Telecommunications Forum, TELFOR 2024

作者： Shyam, Shilpa Paoli, Gerhard Rizkalla, Shrief Auinger, Bernhard Dorda, Antonius Jeurissen, Dennis Scherr, Wolfgang Carinthia University of Applied Sciences Department of Integrated Systems and Circuit Design Villach Austria Research Unit Coexistence & Electromagnetic Compatibility Silicon Austria Labs Graz Austria Business Line Advanced Analog Nxp Semiconductors Austria GmbH & Co Kg Gratkorn Austria

ISBN: (纸本)9798350391053

In the realm of system level design and verification of complex communication systems, several modeling and simulation tools play a crucial role. Among which, Real Number Modeling is of prime importance. In the process of complex modeling, the shift-left paradigm allows testing and validation in an earlier phase and leads to a higher quality system, with reduced cost and shorter development cycles. Real Number Modeling is capable of handling mixed-signal simulations with both digital and analog elements in the same discrete event environment. This paper deals with identifying modeling paradigms in IEEE 1666 (SystemC), with speed as the prime *** investigation covers three primary aspects - the first being a comprehensive comparison of speed performance in models, ranging from complex to simple executed in SystemC DE (Discrete Event), SystemC TDF (Timed Data Flow) and both (TDF+DE). The analysis begins with a complex scenario such as that of a Receiver and further breaks down to simpler ones such as a Low Noise Amplifier. In both cases a mixed model (TDF+DE) is observed to be the fastest. The second aspect deals with analysing the behaviour of SystemC DE and TDF with M number of connected modules in chain and parallel setups. TDF approach is seen to have a performance advantage here, provided the modules are connected to a single source. The third aspect details on factors experimented to save computation time while modeling a system. Among which, the use of datatype converters and number of modules in a cluster are the evaluated elements. Results discussed in the paper show that there are still undiscovered, yet considerable opportunities for improvement in this domain. © 2024 IEEE.

关键词： Low noise amplifiers

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Optimization of a CCM Steady State Boost Converter Power Supply for a Biomedical Sensor

Optimization of a CCM Steady State Boost Converter Power Sup...

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IEEE International Conference on Engineering Veracruz (ICEV)

作者： Roberto B. Cardenas-Ruvalcaba Jose L. Chavez-Hurtado Cuauhtemoc R. Aguilera-Galicia Esteban Martinez-Guerrero Department of Electronics Systems and Informatics Research Group on Integrated Circuit Design ITESO - The Jesuit University of Guadalajara Tlaquepaque Mexico

Applications of the boost converter are becoming more popular in portable biomedical systems because they need to increase the input voltage coming from a small LR 44 battery or other source. This work presents a procedure for optimizing a boost converter power supply for a biomedical sensor. The initial design is obtained by using a first-grade model to calculate the boost converter components, then an optimization procedure is applied based on the Nelder Mead algorithm, which is performed using a Matlab – LTspice driver. Values of the inductor and capacitor, as well as the boost converter's duty cycle and switching frequency are used as optimization variables. design specifications include the average and ripple input current, the average and ripple output voltage, and the output current and its ripple. Results show a trade-off between the output voltage and the input current of the boost converter topology presented. At the end of the optimization process, the best component values are selected based on the electrical parameters that meet the specifications.

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6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction 8

6-bit 1-GS/s Partially Active Flash ADC with Comparator Offs...

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8th IEEE International Symposium on Smart Electronic systems, iSES 2022

作者： Sharma, Nidhi Hande, Vinayak Srivastava, Rajesh Kumar Das, Devarshi Mrinal Indian Institute of Technology Ropar Department of Electrical Engineering Rupnagar India Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria Semi-conductor Laboratory S.A.S Nagar India

ISBN: (纸本)9798350399226

This paper presents a low-power 6-bit 1 GS/s partially active flash analog-to-digital converters (ADC) in 65-nm CMOS technology. A novel comparator offset correction technique is proposed, which does not require additional foreground calibration cycles. The partially active second-stage comparison is employed for power efficiency. A third-stage comparison is introduced for offset correction using fifteen low-offset comparators, out of which two are activated. The 0.5-bit redundancy from the first-stage provides the tolerance to track-and-hold (T/H) buffer settling error for high-speed applications. The simulation results show that the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 36.36 dB and a spurious-free dynamic range (SFDR) of 48.65 dB at a Nyquist frequency of 500 MHz with the power consumption of 13.98 mW. © 2022 IEEE.

关键词： Comparators (optical)

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