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A virtual reality intervention to improve formal caregivers’ understanding of community-dwelling people with dementia: a pilot study

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Contemporary Nurse 2023年第4-5期59卷 334-343页

作者： Tsai, Chia-Mei Hsu, Tzu-Chi Hsieh, Chia-Jung National Taipei University of Nursing and Health Sciences Instructor Nursing College of Fooyin University Taiwan Department of Integrated Circuit Design and Automation Innovation Frontier Institute of Research for Science and Technology National Taipei University of Technology Taiwan School of Nursing College of Nursing National Taipei University of Nursing and Health Sciences Taiwan

Background: The optimum approach to enhance the understanding toward dementia is to experience how patients feel as they experience the manifestations of the disease. The application of virtual reality (VR) and relevant innovative technologies for developing caregiver training programs allows caregivers to better understand dementia and empathize with patients. Objectives: To develop a VR-based experiential training course on individualized care for the behavioral and psychological symptoms of dementia (BPSD). Methods: The participants were caregivers of patients with dementia. They assessed the usability of the VR product after the intervention and the VR experience as a preliminary measure of the effectiveness of the intervention using a usability scale and a self-reported appraisal scale, respectively. Results and Conclusion: Ten in-service and in-home caregivers completed the VR training course. The course yielded a usability score of 74.06 points, indicating excellent usability. The content validity index (CVI) of the self-reported VR experience appraisal scale ranged from 0.8–1, scale-level CVI was 0.81, and reliability (Cronbach’s α) was 0.929. The mean score of the overall scale was 4.67 ± 0.33. These findings suggest that the VR-based experiential training course enabled the home caregivers to deepen their understanding of the BPSD shown by community-dwelling patients and, therefore, to provide better care services. The course developed in this study is the first VR course directed toward dementia care in Taiwan. Given its excellent usability, as well as the effectiveness of the VR experience appraisal scale for deepening the caregivers’ skills in managing patients’ BPSD symptoms, the course can be promoted and applied in caregiver training programs for dementia in the future. © 2023 Informa UK Limited, trading as Taylor & Francis Group.

关键词： caregiver dementia care virtual reality

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BAG2 Assisted Hierarchical Analog Layout Synthesis for Planar Technologies

BAG2 Assisted Hierarchical Analog Layout Synthesis for Plana...

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Austrian Workshop on Microelectronics (Austrochip)

作者： Matthew Bio Wolfgang Scherr A. S. Agbemenu Santiago Martin Sondón Johannes Sturm Vinayak Hande Josef Ressel Centre for System-on-Chip Design Automation Carinthia Institute for Microelectronics Carinthia University of Applied Sciences Department of Computer Engineering Kwame Nkrumah University of Science and Technology Kumasi Ghana Department of Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria

Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continued to be developed targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley analog generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a process-independent flow as well as encourages design re-use due to using parameterized generators which can be scaled as required and this reduces the layout-development time compared to manual hand-made layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65nm and Cadence GPDK 45nm processes. A case study is made with a number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.

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An adaptive single event upset (SEU)-hardened flip-flop design

An adaptive single event upset (SEU)-hardened flip-flop desi...

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2019 IEEE International Conference on Electron Devices and Solid-State circuits, EDSSC 2019

作者： Zhang, Man Guo, Zhongjie Xu, WanCheng Department of Integrated Circuit Design Institute of Microelectronics Technology Xi'an China School of Automation and Information Engineering Xi'an University of Technology Xi'an China

ISBN: (纸本)9781728102863

In this paper, a new radiation hardened flip-flop design technique is proposed. The structure provides an possibility that the D-type flip-flop can be configured as an Single Event Upset (SEU) hardened or non-hardened flip-flop in a circuit based on the logic states of the sensitive nodes with RC filtering structure being involved or not, considering speed and reliability. The proposed structure makes itself more widely used in both space, defense applications and high-performance terrestrial applications. Spice simulation results show that the flip-flop has good performance of SEU-hardness and flexibility. © 2019 IEEE.

关键词： Radiation hardening

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Synthetic gene circuits moving into the clinic

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Quantitative Biology 2021年第1期9卷 100-103页

作者： Shuguang Peng Huiya Huang Ping Wei Zhen Xie MOE Key Laboratory of Bioinformatics and Bioinformatics Division Center for Synthetic and System BiologyDepartment of AutomationBeijing National Research Center for Information Science and TechnologyTsinghua UniversityBeijing 100084China Beijing Syngentech Co. LtdZhongguancun Life Science ParkChangping DistrictBeijing 102206China Center for Gene Circuit and Cell Design Shenzhen Institute of Synthetic BiologyShenzhen Institutes of Advanced TechnologyChinese Academy of SciencesShenzhen 518055ChinaCenter for Quantitative BiologyAcademy for Advanced Interdisciplinary StudiesPeking UniversityBeijing 100871China

On November 28th 2020,SyngenTech,a China-based biotechnology company,announced that the company’s leading oncolytic virotherapeutic product,SynOVl.l,was approved for clinical trial by the *** and Drug *** synthetic bacterial or cell therapy[1,2],this is the first introduction of a viral therapy engineered using synthetic gene circuits into the *** with the clinical development of variable living therapeutics,we anticipate that synthetic gene circuits will receive increasing attention as a revolutionary technology to improve disease-treatment efficacy.

关键词： clinic clinical Together

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High efficiency power management system for solar energy harvesting applications

High efficiency power management system for solar energy har...

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Asia-Pacific Conference on circuits and Systems

作者： Chang, Ming-Hung Wu, Jung-Yi Hsieh, Wei-Chih Lin, Shang-Yuan Liang, You-Wei Wei, Hwang Department of Electronics Engineering Institute of Electronics National Chiao Tung University Hsin-Chu 300 Taiwan Circuit Design Department Design Automation Technology Division Industrial Technology Research Institute Hsin-Chu 300 Taiwan

ISBN: (纸本)9781424474561

A high efficiency power management system for solar energy harvesting applications is proposed. The power management system receives power from photovoltaic (PV) cell and generate different voltage levels, they are 1V∼0.3V for analog circuitry and low power digital circuitry, -1.2V for super-cutoff technique in memory circuitry, and 10V for FLASH memory or I/O components. The great voltage varieties are suitable for green integrated regulator SoC electronics. The power management system also contains a rechargeable battery which is charged by multi-phase maximum power tracking (MPT) circuitry with the PV cell module. With the MPT circuitry, the power of PV cell can be regulated in the maximum power region. The average power efficiency of the MPT circuitry is up to 80%∼73%. All results are simulated in UMC 90nm bulk CMOS technology model. © 2010 IEEE.

关键词： Solar energy

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Optimized layout on ESD protection diode with low parasitic capacitance

Optimized layout on ESD protection diode with low parasitic ...

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2010 10th IEEE International Conference on Solid-State and Integrated circuit Technology

作者： Yeh, Chih-Ting Ker, Ming-Dou Circuit Design Department Design Automation Technology Division Industrial Technology Research Institute Hsinchu Taiwan Institute of Electronics National Chiao-Tung University Hsinchu Taiwan Department of Electronic Engineering I-Shou University Kaohsiung Taiwan

ISBN: (纸本)9781424457984

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved. ©2010 IEEE.

关键词： CMOS integrated circuits

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Optimized Layout on ESD Protection Diode with Low Parasitic Capacitance

Optimized Layout on ESD Protection Diode with Low Parasitic ...

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2010 10th IEEE International Conference on Solid-State and Integrated circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Chih-Ting Yeh Ming-Dou Ker Circuit Design Department Design Automation Technology Division Information and Communications Res Institute of Electronics National Chiao-Tung University Hsinchu Taiwan Department of Electronic E

ISBN: (纸本)9781424457977

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multiwaffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved.

关键词： Electrostatic discharge Layout Junctions Iterative closest point algorithm Transmission line measurements Current measurement Capacitance

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Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

Layout optimization on ESD diodes for giga-Hz RF and high-sp...

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International Symposium on VLSI design, automation and Test

作者： Chih-Ting Yeh Yung-Chih Liang Ming-Dou Ker Institute of Electronics National Chiao Tung University Hsinchu Taiwan Circuit Design Department Design Automation Technology Division Information and Communications Research Laboratories Industrial Technology Research Institute Hsinchu Taiwan Department of Electronic Engineering I-Shou University Kaohsiung Taiwan

ISBN: (纸本)9781424452699;9781424452712

The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

关键词： Electrostatic discharge Diodes Radio frequency Protection Parasitic capacitance Robustness CMOS integrated circuits Current distribution RF signals Degradation

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A new three-dimensional capacitor model for accurate simulation of parasitic capacitances in nanoscale MOSFETs

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IEEE Transactions on Electron Devices 2009年第8期56卷 1598-1607页

作者： Guo, Jyh-Chyurn Yeh, Chih-Ting Department of Electronics Engineering National Chiao Tung University Hsinchu 300 Taiwan Design Automation Technology Division Department of Circuit Design Industrial Technology Research Institute Hsinchu 31040 Taiwan

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance Cof dominates around 25% of the intrinsic gate capacitance (Cgint) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C of/Cgint above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design. © 2009 IEEE.

关键词： Nanotechnology

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The enhancement of power-rail ESD clamp circuit with gate-substrate-triggered technique

The enhancement of power-rail ESD clamp circuit with gate-su...

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International Symposium on Physical & Failure Analysis of Integrated circuits

作者： Chih-Ting Yeh Yung-Chih Liang Zhe-Wei Jiang Xin-Yuan Chang Circuit Design Department Design Automation Technology Division SoC Technology Center Industrial Technology and Research Institute Hsinchu Taiwan

In this work, the power-rail ESD clamp circuit fabricated in 130 nm CMOS process is investigated. In order to improve the ESD protection ability, the power-rail ESD clamp circuit with gate-substrate-triggered is proposed. By comparing with the other two techniques, gate-driven and substrate-triggered, it is shown that the secondary breakdown current of the power-rail ESD clamp circuit with gate-substrate-triggered is improved by 20%.

关键词： Electrostatic discharge Clamps MOS devices Protection CMOS technology circuit testing Stress Substrates Robustness Voltage

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