The free market forces infrastructure operators to increase their operational efficiency. To achieve this, among other things personnel costs have to be reduced. This implicates the reduction of the number of train st...
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The free market forces infrastructure operators to increase their operational efficiency. To achieve this, among other things personnel costs have to be reduced. This implicates the reduction of the number of train station inspectors. Since they were also responsible for checking the passing trains for fault states, the higher distances of unobserved movement of trains result in higher risks of heavy accidents. On the other hand, there were numerous developments of new sensor-systems for checking the mentioned train fault states. Unfortunately, all of these systems focus only on singular or at least on several particular deviations from normal and are completely stand-alone solutions. At higher passing speeds the accuracy and the reliability of these systems varies in a wide range. This is an important reason why today's fault-checking sensor systems are only used for alarming manned train guidance stations. Taking these trends into account, the demand for an overall train inspection system is obvious and resulted in a research project called "Checkpoint", which is funded by the Austrian government. Our approach is based on the acquisition of all relevant train properties to get knowledge of the complete train condition for better failure estimation. Thus, a concept for efficient integration of commercially available sensor systems and for universal data treatment was developed. It enables easy configuration of the data analysis and definition of fail-states by a rule based mechanism. The main technical innovation of the system comes from the direct connection to the interlocking system via the control system, which offers the ability to intervene automatically in case of a detected failure (e.g. stopping the train). To determine the reliability of new sensor systems under realistic conditions a prototype of a Checkpoint was built up and the most relevant sensor systems (hot box detector, flat wheel detector, dynamic scale and loading gauge detector) were integrated
In this paper a methodology for verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters. This model allows us to define formal specifications at each level of abstraction a...
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We outline a general methodology for the formal verification of instruction pipelines in RISC cores. The different kinds of conflicts, i. e. resource, data and control conflicts, that can occur due to the simultaneous...
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Active magnetic bearing (AMB) actuators support rotors without friction but require feedback control for stabilization and performance. We address the application of modern control techniques such as LQG/LTR, H/spl in...
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The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN ...
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The paper describes an analog current mode realization of Discrete-Time Cellular Neural Networks (DTCNNs) with high cell density, which have local analog and local logic memory. Hence, some important parts of the CNN Universal Machine concept are implemented. The computation speed can be adjusted simply to the application by changing the clock rate. The circuit components are described in detail and SPICE level 2 simulation results are given for the ORBIT 2.0 /spl mu/m process. A layout has been designed for a chip with 12 by 12 cells on a square grid realizing a one-neighborhood with 9 feedback and 9 control coefficients. The cell size is 619 /spl mu/m by 425 /spl mu/m and the simulated speed is between 1 MHz and 10 MHz depending on the minimum value of the state current. For the latter this leads to a simulated performance of 25.9 10/sup 9/ XPS for a single chip operation with an effective area of 0.379 cm/sup 2/ and a worst case power consumption of 0.86 W. Another important feature of the chip is its capability for a spatial cascaded connection.< >
A general methodology, based on a hierarchical model of interpreters, is presented for formally verifying RISC cores. The abstraction levels used by a designer in the implementation of RISC cores, namely the instructi...
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A general methodology, based on a hierarchical model of interpreters, is presented for formally verifying RISC cores. The abstraction levels used by a designer in the implementation of RISC cores, namely the instruction set level, the pipeline stage level, the phase level and the hardware implementation, are mirrored by this hierarchical model. The use of this model allows us to successively prove the correctness between two neighboring levels of abstractions, so that the verification process is simplified. The parallelism in the execution of the instructions, resulting from the pipelined architecture of RISCs is handled by splitting the proof into simplified steps. The first step shows that, under certain assumptions, no conflicts can occur between simultaneously executed instructions, and the second step shows that each instruction is implemented correctly by the sequential execution of its pipeline steps.< >
In this paper a new test schedule problem is described and an algorithm for its solution is presented. Hardware overhead and test application time is saved by executing tests in parallel, when BIST (built-in-self-test...
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In this paper a new test schedule problem is described and an algorithm for its solution is presented. Hardware overhead and test application time is saved by executing tests in parallel, when BIST (built-in-self-test) structures are integrated on the chip. The authors achieve a reduction in the bit width of the control signals and the global area of the controller by merging the test control graph and the control graph for the data path into one control graph. This control graph can be globally optimized by the controller synthesis system CASTOR.< >
A new integrated circuit cellular neural network (CNN) implementation having digitally or continuously selectable template coefficients is presented. Local logic and memory are added into each cell providing a simple ...
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A new integrated circuit cellular neural network (CNN) implementation having digitally or continuously selectable template coefficients is presented. Local logic and memory are added into each cell providing a simple dual (analog and digital) computing structure. The variable-gain operational transconductance amplifiers (OTAs) are used as the voltage controlled current sources to program the template element values. This analog array processor can be applied to solve problems with a sequence of different templates. A 4-by-4 CNN circuit is realized using the 2- mu m analog CMOS process. To test the circuit a general purpose control system was designed with the microcomputer interface.< >
In this article, the use of Multiple Input Signature Registers (MISRs) as random pattern generators is investigated. This additional function helps to reduce hardware overhead and testing time, when BIST (Built-In Sel...
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In this article, the use of Multiple Input Signature Registers (MISRs) as random pattern generators is investigated. This additional function helps to reduce hardware overhead and testing time, when BIST (Built-In Self-Test) structures are integrated on the chip, because the MISR can at the same time generate test patterns and collect test responses. A formula is presented, which determines the number of clock cycles needed to generate a given number of random patterns. Finally we suggest a method for how the number of test patterns can be reduced when the MISR acts as test pattern generator and compressor in a feedback loop.
作者：
DUNIETZ, ISHSU, JLCMCEACHERN, MTSTOCKING, JHSWARTZ, MATROMBLY, RMThe authors
Irwin S. Dunietz John L.C. Hsu Michael T. McEachern James H. Stocking Mark A. Swartz andRodney M. Tromblyare responsible for design and development of the Manufacturing Process Control System. Mr. Dunietz joined AT&T in 1980. He is a member of the technical staff in the Manufacturing Information Automation department at AT&T Engineering Research Center Princeton New Jersey. He received an A.B. in mathematics from Cornell University and an M.S.E. in computer science from Princeton University. Mr. Hsu who joined AT&T in 1970 is a department head in the Manufacturing Information Automation department at the Engineering Research Center. He received an M.S. in electrical engineering from the University of Missouri. Mr. McEachern joined AT&T in 1962 and is a supervisor in the 5ESS™ Line Unit Manufacturing department at AT&T Technologies in Oklahoma City Oklahoma. He is responsible for the manufacturing process control center in Oklahoma City which provides computerized support for all circuit pack manufacturing. Mr. Stocking who joined AT&T in 1975 is a supervisor in the Manufacturing Information Automation department at the Engineering Research Center. He received a B.S. in chemical engineering from Rensselaer Polytechnic Institute and a Ph.D. in chemical engineering from the University of California Berkeley. Mr. Swartz joined AT&T in 1980 and is a member of the technical staff in the Manufacturing Information Automation department at the Engineering Research Center. He received an A.B. in computer science from Cornell University and an M.S. in computer science from Rutgers—The State University. Mr. Trombly who joined AT&T in 19 78 is an assistant manager at the AT&T Merrimack Valley Works in Massachusetts. Previously he was a supervisor at the Engineering Research Center. He holds a B.S. in computers and systems engineering and an M.S.E.E. from Rensselaer Polytechnic Institute.
The central challenge of all manufacturing is making products to the right standards and delivering them at the right time. AT&T is upgrading its corporate and factory resource planning systems to improve control ...
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The central challenge of all manufacturing is making products to the right standards and delivering them at the right time. AT&T is upgrading its corporate and factory resource planning systems to improve control of day-to-day manufacturing. The Manufacturing Process Control System (MPCS), developed at the AT&T Engineering Research Center (ERC), provides this support. MPCS connects the shop floor with production scheduling, accounting, product data archive, and engineering support systems.
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