This work introduces AmIVital, a Spanish project which aims to provide a platform that meets the bases of AAL (Ambient Assisted Living) and facilitates the development of applications and business models for an emergi...
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Hardware components can contain hidden backdoors, which can be enabled with catastrophic effects or for ill-gotten profit. These backdoors can be inserted by a malicious insider on the design team or a third-party IP ...
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Hardware components can contain hidden backdoors, which can be enabled with catastrophic effects or for ill-gotten profit. These backdoors can be inserted by a malicious insider on the design team or a third-party IP provider. In this paper, we propose techniques that allow us to build trustworthy hardware systems from components designed by untrusted designers or procured from untrusted third-party IP providers. We present the first solution for disabling digital, design-level hardware backdoors. The principle is that rather than try to discover the malicious logic in the design -- an extremely hard problem -- we make the backdoor design problem itself intractable to the attacker. The key idea is to scramble inputs that are supplied to the hardware units at runtime, making it infeasible for malicious components to acquire the information they need to perform malicious actions. We show that the proposed techniques cover the attack space of deterministic, digital HDL backdoors, provide probabilistic security guarantees, and can be applied to a wide variety of hardware components. Our evaluation with the SPEC 2006 benchmarks shows negligible performance loss (less than 1% on average) and that our techniques can be integrated into contemporary microprocessor designs.
While providing correct functionality has been the thrust of most software design efforts, embedded software poses several additional challenges. Among them is designing robust software which can tolerate inaccurate i...
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ISBN:
(纸本)9781450305594
While providing correct functionality has been the thrust of most software design efforts, embedded software poses several additional challenges. Among them is designing robust software which can tolerate inaccurate inputs (coming from degraded sensors), failure of software components, and wearing-out of electro-mechanical parts it controls. For this, a design space exploration is performed and several design options are evaluated for their ability to tolerate quality (or accuracy degradation) faults. While a model-based approach enables an early analysis of quality faults, modeling and analyzing the effects of quality faults is a challenge. In this work we propose a quality fault-tolerance analysis framework which is used on operation-level models of embedded software, and an abstraction of quality-faults suitable for this analysis. The proposed method consists of characterizing individual components of the model, and then using the pre-characterized behaviors to quickly evaluate the software design. Characterization is a one-time effort and results of the same can be reused when a new design is evaluated. This results in additional speedup of upto 6-10× faster evaluation of designs, thereby facilitating a quick early evaluation of design options.
Accurately monitoring changing energy usage patterns in households is a first requirement for more efficient and eco-friendly energy management. Such data is essential to the establishment of the Smart Grid, but at th...
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Sink Scheduling, in the form of scheduling multiple sinks among sink sites to leverage traffic burden, is an effective mechanism for the energy-efficiency of wireless sensor networks (WSNs). Due to the inherent diffic...
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The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frame...
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Uncertainty handling is a major issue for the control of real-world systems. Traditional singleton type-1 Fuzzy Logic Controllers (FLCs) with crisp inputs and precise fuzzy sets cannot fully cope with the high levels ...
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Uncertainty handling is a major issue for the control of real-world systems. Traditional singleton type-1 Fuzzy Logic Controllers (FLCs) with crisp inputs and precise fuzzy sets cannot fully cope with the high levels of uncertainties present in real world environments (e.g. sensor noise, environmental impacts, etc.). While non-singleton type-1 fuzzy systems can provide an additional degree of freedom through non-singleton fuzzification of the inputs, it is unclear how this capability relates to singleton type-1 and specifically interval type-2 FLCs in terms of control performance (also because the application of non-singleton type-1 FLCs is quite rare in the literature). In recent years interval type-2 FLCs employing type-2 fuzzy sets with a Footprint of Uncertainty (FOU) have become increasingly popular. This FOU provides an additional degree of freedom that can enable type-2 FLCs to handle the uncertainties associated with the inputs and the outputs of the FLCs. One of the main criticisms of singleton type-2 FLCs is that they outperform (the usually singleton-) type-1 FLCs because they - respectively their type-2 fuzzy sets, employ extra parameters, thus making improved performance an obvious result. In order to address this criticism, we have implemented a non-singleton type-1 FLC which allows a more direct comparison between the non-singleton type-1 FLC and singleton interval type-2 FLC as the number of parameters for both controllers is very similar. The paper details the implementation details of the FLCs for the application of a nonlinear servo system and provides the experimental simulation results which were performed to study the effect of increasing levels of uncertainty (in the form of input noise) and the capability of the individual FLCs to cope with them. We conclude by providing our interpretation of the results and highlighting the essential differences in the uncertainty handling between the (non-) singleton type-1 and singleton interval type-2 FLC
Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the ...
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Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design of an embedded MPSoC is usually customized to the requirements of the application domain. The need for fast time to market of new embedded MPSoC designs calls for a rapid design flow of the included customized processors. This paper proposes a Multicore Application-Specific Instruction Set Processor (MCASIP) co-design flow that exploits parallel programming languages as the application description format. The designer can capture the parallelism of the algorithm and exploit specialized instructions using a single high-level programming language. Parallelism of the designed MCASIP architectures can be scaled both at instruction and task levels, enabling easy exploration of the MCASIP design space. This paper describes the design flow and its key technical challenges, and demonstrates its scalability potential. The presented preliminary results show promise for an efficient multiprocessor design methodology.
Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can ...
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