Dataflow predication provides a lightweight full support for predicated execution in dataflow-like architectures. One of its major overhead is the large amounts of fanout trees for distributing predicates to all depen...
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In this paper, we describe the formatting guidelines for ACM SIG Proceedings. Traditionally silence in VoIP applications is detected by a VAD algorithm after G.729 compression, both have high computational and energy ...
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The purpose of this paper is to explore the collaborative planning and design process of an innovative future school. Our case study examined, modeled, and further developed this planning and design process aiming to ...
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ISBN:
(纸本)9789512295470
The purpose of this paper is to explore the collaborative planning and design process of an innovative future school. Our case study examined, modeled, and further developed this planning and design process aiming to create a more wide-ranging place and space for learning than a mere school building We wanted to find out what kind of collaboration and network management would support the participatory planning and design process, and how it would be possible to make children's and youth's opinions visible and to accomplish collaboration in the design process. The case data was collected from a SimLab™ simulation project and architecture workshops. Our findings indicate that that the process of planning and designing innovative future schools require seamless collaboration between various actors and stakeholders, such as architects, pedagogy experts, future school users, and municipal decision makers. Furthermore, the network management aspect should be taken into account to make the collaborative design process more fruitful. Especially, the role of boundary objects was observed to be important both for supporting collaboration and participation in the design process, and for making children 's and youth's opinions visible.
Energy efficiency has become an important concern for the design of communication systems, particularly the wireless sensor networks where recharging battery might not be feasible. In this paper, we investigate how er...
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In this paper we analyse the resilience of a peer-to-peer (P2P) evolutionary algorithm (EA) subject to the following dynamics: computing nodes acting as peers leave the system independently from each other causing a c...
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In this paper we present the Gossip-based Evolvable Agent Model (GossEvAg) within the context of parallel fine-grained Evolutionary Algorithms (EAs). It extends the Cellular Evolutionary Algorithm (CEA) definition wit...
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In this paper we present the Gossip-based Evolvable Agent Model (GossEvAg) within the context of parallel fine-grained Evolutionary Algorithms (EAs). It extends the Cellular Evolutionary Algorithm (CEA) definition with two novel features designed to work on Peer-to-Peer (P2P) networks: every individual is self-scheduled in a single thread and dynamically self-organizes its neighbourhood via newscasting, a gossip protocol. As a consequence of such multi-threading model, each Evolvable Agent (EvAg) updates asynchronously its state at random depending on the underlying platform scheduler. In order to assess the effects of asynchrony and the gossip protocol, we perform an experimental evaluation of the model for a set of discrete optimization problems. As a baseline for comparison we use two canonical genetic algorithms (GA): A steady-state GA (ssGA) and a generational GA (gGA). We also test two more topologies for the EvAg, a complete graph topology which allows panmixia and a Watts-Strogatz topology which has shown good theoretical and empirical results in related papers. We found that leaving the management of the EvAg to the underlying platform scheduler has an interesting emerging feature: the model is able to scale seamlessly in desktop computers without any effort from the practitioner. We measure how the algorithm speed scales by conducting the experiments in a Single and a Dual-Core Processor architectures.
On today's microprocessors, there often exist several different types of registers, e.g. general purpose registers and floating point registers. A given program may use one type of registers much more frequently t...
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ISBN:
(纸本)9781605581583
On today's microprocessors, there often exist several different types of registers, e.g. general purpose registers and floating point registers. A given program may use one type of registers much more frequently than other types. This creates an opportunity to employ the infrequently used registers as spill destinations for the more frequently used register types. In this paper, we present a code optimization method named idle register exploitation (IRE) to exploit such opportunities. We developed a model, called the IRE model, or IREM, to determine the static performance gains of IRE versus spilling to the stack. On a microprocessor with fast data paths between different types of registers, we find that IRE method speeds up the execution of the SPECint benchmark suite from 1.7% to 10%. In contrast, on microprocessors with less efficient data transfer paths, the performance gain is limited. In some cases, performance may even suffer degradation. This result argues strongly for the adoption of fast data paths between different types of registers for the purpose of reducing register spills, which is important in view of the increased significance of memory bottlenecks on future microprocessors. Copyright 2008 ACM.
In this paper a generic parallel procedure for dynamic problems using evolutionary algorithms is presented. In dynamic multi-objective problems, the objective functions, the constraints and hence, also the solutions, ...
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Selective attention to visual or auditory stimuli that elicits steady-state visual or auditory responses (SSVEP or ASSR respectively) amplifies the power of those flickering frequencies of the stimuli measured in the ...
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Selective attention to visual or auditory stimuli that elicits steady-state visual or auditory responses (SSVEP or ASSR respectively) amplifies the power of those flickering frequencies of the stimuli measured in the electroencephalography (EEG). The design of brain-computer interfaces (BCI) based on selective attention to auditory stimuli that elicits ASSRs has two major advantages: First, no much training is needed as selective attention is an inherent skill of human beings. Second, as the human hearing system behaves as an amplitude modulated (AM) envelope detector, if the auditory stimuli are previously AM modulated, a steady-state response signal can be easily elicited. As EEG signals are considered to be non stationary, this is an interesting approach to EEG analysis as the feature of our interest can be considered stationary, hence Fourier analysis applied. In this paper we study the behavior of a perceptron as a classifier of a BCI system where the features for classification are extracted from EEG as responses to AM modulated auditory stimuli and how we can use it in a BCI system.
To strengthen the writing of Junior and Senior Electrical and computer Engineering students, we are adding several writing assignments based upon the Five Paragraph Essay format to our Junior and Senior courses. The l...
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