We propose a simulation-based method in the verification of SoC bus system. By the method, constrained-random vector is used to make simulation first;then a coverage analysis is made in the simulation process until a ...
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We propose a simulation-based method in the verification of SoC bus system. By the method, constrained-random vector is used to make simulation first;then a coverage analysis is made in the simulation process until a certain coverage statistics is obtained. Finally, the test vector is manually generated. We use this method to verify a SoC system and get a satisfactory result by reducing the time of simulation effectively.
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can reduce the penalty of mis-speculations b...
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Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can reduce the penalty of mis-speculations by re-executing only instructions affected by the mis-speculation, instead of all instructions. In this paper we introduce a new selective re-execution mechanism that exploits the properties of a dataflow-like Explicit Data Graph Execution (EDGE) architecture to support efficient mis-speculation recovery, while scaling to window sizes of thousands of instructions with high performance. This distributed selective re-execution (DSRE) protocol permits multiple speculative waves of computation to be traversing a dataflow graph simultaneously, with a commit wave propagating behind them to ensure correct execution. We evaluate one application of this protocol to provide efficient recovery for load-store dependence speculation. Unlike traditional dataflow architectures which resorted to single-assignment memory semantics, the DSRE protocol combines dataflow execution with speculation to enable high performance and conventional sequential memory semantics. Our experiments show that the DSRE protocol results in an average 17% speedup over the best dependence predictor proposed to date, and obtains 82% of the performance possible with a perfect oracle directing the issue of loads. Copyright 2004 ACM.
An analysis of the data dependencies in the Conjugate Gradient iterative method for the solution of narrow band systems is performed in order to develop and implement a mixed OpenMP-MPI code which takes into account t...
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Prediction of the secondary structure of a protein from its aminoacid sequence remains an important and difficult task. Up to this moment, three generations of Protein Secondary Structure Algorithms have been defined:...
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In this paper we present a new approach for the problem of approximating a function from a training set of I/O points using fuzzy logic and fuzzy systems. Such approach, as we will see, will provide us a number of adv...
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This work in progress describes the development of remote lecture demonstrations and experiments for communication engineering. The remote panel feature of LabVIEW is used to allow access to Virtual Instruments (VP...
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Adaptation is one of the necessary capabilities of any expert system. In a traditional expert system, the evolving environment is often treated in a static view. And the system accepts the change negatively. Our focus...
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ISBN:
(纸本)0780386531
Adaptation is one of the necessary capabilities of any expert system. In a traditional expert system, the evolving environment is often treated in a static view. And the system accepts the change negatively. Our focus in this paper is to construct an adaptive CBR model which can learn continually through detecting feedbacks from the outside to partially release this. Knowledge base here is improved gradually so to enhance the system's adaptation of solving problems in dynamic environment.
In this paper, the multigrid-based fuzzy system (MGFS) approach is applied for the CATS time series prediction benchmark. The MGFS architecture overcomes the problem inherent to all grid-based fuzzy systems when deali...
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In this paper, the multigrid-based fuzzy system (MGFS) approach is applied for the CATS time series prediction benchmark. The MGFS architecture overcomes the problem inherent to all grid-based fuzzy systems when dealing with high dimensional input data, thus keeping low computational cost and high performance. A greedy algorithm for MGFS structure identification allows to perform the input variable selection for the time series prediction problem, while identifying the pseudo-optimal architecture according to the provided dataset.
The goal of this paper is to achieve real time control of a monotonic system which, in general, may be non-linear and whose differential equations are unknown. We assume that there is no model of the plant available s...
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The goal of this paper is to achieve real time control of a monotonic system which, in general, may be non-linear and whose differential equations are unknown. We assume that there is no model of the plant available so there cannot be any off-line pre-training of the main controller parameters. We propose a both adaptive and self-learning algorithm capable of starting from a "void" fuzzy controller and, in real time, optimizing the fuzzy controller's rules (both antecedents and consequents) in order to translate the state of the plant to the desired value in the shortest possible time.
technology trends present new challenges for processor architectures and their instruction schedulers. Growing transistor density increases the number of execution units on a single chip, and decreasing wire transmiss...
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ISBN:
(纸本)9780769522296
technology trends present new challenges for processor architectures and their instruction schedulers. Growing transistor density increases the number of execution units on a single chip, and decreasing wire transmission speeds causes long and variable on-chip latencies. These trends severely limit the two dominant conventional architectures: dynamic issue superscalars, and static placement and issue VLIWs. We present a new execution model in which the hardware and static scheduler instead work cooperatively, called static placement dynamic issue (SPDI). This paper focuses on the static instruction scheduler for SPDI. We identify and explore three issues SPDI schedulers must consider - locality, contention, and depth of speculation. We evaluate a range of SPDI scheduling algorithms executing on an explicit data graph execution (EDGE) architecture. We find that a surprisingly simple one achieves an average of 5.6 instructions-per-cycle (IPC) for SPEC2000 64-wide issue machine, and is within 80% of the performance without on-chip latencies. These results suggest that the compiler is effective at balancing on-chip latency and parallelism, and that the division of responsibilities between the compiler and the architecture is well suited to future systems.
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