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2003 IEEE International Symposium on Computational Intelligence for Measurement Systems and Applications, CIMSA 2003

作者： Rojas, I. Pomares, H. Puntonet, C.G. Rojas, F. Rodríguez, M. Valenzuela, O. Department of Architecture and Computer Technology University of Granada Spain Department of Applied Mathematics University of Granada Spain

ISBN: (纸本)0780377834

When confronted with a control problem for a complicated physical process, a control engineer generally follows a relatively systematic design procedure. In this paper we design an on-line controller which is able to modify and adapt the rule base of the system with just only qualitative knowledge about the plant to be controlled. In our example, the system is an helicopter, and the objective is to control the altitude of the helicopter, when the mass of the system change, or other parameters defining the helicopter has been modified. © 2003 IEEE.

关键词： Fuzzy control

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Vector quantization for simulation modeling of queuing systems

Vector quantization for simulation modeling of queuing syste...

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6th International Conference on Telecommunication in Modern Cable, Satellite and Broadcasting Services

作者： Radev, D Radeva, S Depatment of Communication Technique and Technology University of Rouse Bulgaria Department of Computer Aided Engineering University of Architecture Civil Engineering and Geodesy Sofia Bulgaria

ISBN: (纸本)0780379632

In this research is applied simulation modeling of queuing systems with the help of vector quantization. A technique for adjusting the boundaries between classes with vector quantization is suggested. With this technique is determined the function of density distribution of the input flow. The implementation of suggested approach for simple Jackson queuing system is shown.

关键词： communication networks queuing theory neural networks vector quantization

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Power signature analysis

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IEEE Power and Energy Magazine 2003年第2期1卷 56-63页

作者： Laughman, Christopher Lee, Kwangduk Cox, Robert Shaw, Steven Leeb, Steven Norford, Les Armstrong, Peter Lab. of Electromagnet. and Electron. Dept. of Elec. and Computer Eng. Montana State University Bozeman MT United States Department of Architecture MIT Department of Electrical Engineering Department of Mechanical Engineering Department of Building Technology

Field tests demonstrated the value of enhancements that enable an advanced nonintrusive load monitoring system to tackle complex monitoring environments. Nonintrusive load monitoring (NILM) can determine the operating schedule of electrical loads in a target system from measurements made at a centralized location, such as the electric utility service entry. In contrast to other systems, NILM reduces sensor costs by using relatively few sensors.

关键词： Electric load forecasting

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Cooperative Co-evolution of multilayer pereeptrons

Cooperative Co-evolution of multilayer pereeptrons

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7th International Work-Conference on Artificial and Natural Neural Networks, IWANN 2003

作者： Castillo, P.A. Arenas, M.G. Merelo, J.J. Romero, G. Department of Architecture and Computer Technology University of Granada Campus de Fuentenueva GranadaE. 18071 Spain

ISBN: (纸本)3540402101

Co-evolution is a posible solution to the problem of simultaneous optimization of artificial neural network and training agorithm parameters, due to its ability to deal with vast search spaces. Moreover, this scheme is recommendable when the optimization problem is decomposable in *** this paper an approach to cooperative co-evolutionary optimisation of multilayer pereeptrons, that improves the G-Prop genetic back-propagation algorithm, is presented. Obtained results show that this co-evolutionary version of G-Prop obtains similar or better results needing much fewer training epochs and thus using much less time than the sequential versions. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Multilayers

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Exploiting microarchitectural redundancy for defect tolerance

Exploiting microarchitectural redundancy for defect toleranc...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Premkishore Shivakumar S.W. Keckler C.R. Moore D. Burger Computer Architecture and Technology Laboratory Department of Computer Sciences University of Technology Austin USA

The continued increase in microprocessor clock frequency that has come from advancements in fabrication technology and reductions in feature size, creates challenges in maintaining both manufacturing yield rates and long-term reliability of devices. Methods based on defect detection and reduction may not offer a scalable solution due to cost of eliminating contaminants in the manufacturing process and increasing chip complexity. We propose to use the inherent redundancy available in existing and future chip microarchitectures to improve yield and enable graceful performance degradation in fail-in-place systems. We introduce a new yield metric called performance averaged yield (Y/sub PAV/), which accounts both for fully functional chips and those that exhibit some performance degradation. Our results indicate that at 250nm we are able to increase the Y/sub PAV/ of a uniprocessor with only redundant rows in its caches from a base value of 85% to 98% using microarchitectural redundancy. Given constant chip area, shrinking feature sizes increases fault susceptibility and reduces the base Y/sub PAV/ to 60% at 50nm, which exploiting microarchitectural redundancy then increases to 99.6%.

关键词： Microarchitecture Redundancy Degradation Microprocessors Clocks Frequency Fabrication Maintenance Manufacturing Costs

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Scalable hardware memory disambiguation for high ILP processors 36

Scalable hardware memory disambiguation for high ILP process...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： S. Sethumadhavan R. Desikan D. Burger C.R. Moore S.W. Keckler Department of Computer Sciences Computer Architecture and Technology Laboratory Department of Electrical and Computer Engineering University of Texas Austin USA

ISBN: (纸本)9780769520438

This paper describes several methods for improving the scalability of memory disambiguation hardware for future high ILP processors. As the number of in-flight instructions grows with issue width and pipeline depth, the load/store queues (LSQ) threaten to become a bottleneck in both power and latency. By employing lightweight approximate hashing in hardware with structures called Bloom filters, many improvements to the LSQ are possible. We propose two types of filtering schemes using Bloom filters: search filtering, which uses hashing to reduce both the number of lookups to the LSQ and the number of entries that must be searched, and state filtering, in which the number of entries kept in the LSQs is reduced by coupling address predictors and Bloom filters, permitting smaller queues. We evaluate these techniques for LSQs indexed by both instruction age and the instruction's effective address, and for both centralized and physically partitioned LSQs. We show that search filtering avoids up to 98% of the associative LSQ searches, providing significant power savings and keeping LSQ searches to under one high-frequency clock cycle. We also show that with state filtering, the load queue can be eliminated altogether with only minor reductions n performance for small instruction window machines.

关键词： Hardware Filtering Filters Delay Scalability Pipelines Out of order computer architecture Laboratories Clocks

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A reconfigurable monitoring system for large-scale network computing

A reconfigurable monitoring system for large-scale network c...

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9th International Euro-Par Conference on Parallel Processing, Euro-Par 2003

作者： Subramanyan, Rajesh Miguel-Alonso, José Fortes, José A.B School of Electrical and Computer Engineering Purdue University West LafayetteIN47907 United States Department of Computer Architecture and Technology The University of the Basque Country UPV/EHU San Sebastian Spain Department of Electrical and Computer Engineering University of Florida GainesvilleFL32611 United States

ISBN: (纸本)354040788X

The dynamic nature of large-size Network Computing Systems (NCSs) and the varying monitoring demands from the end-users pose serious challenges for monitoring systems (MSs). A statically configured MS initially adjusted to perform optimally may end performing poorly. A reconfiguration mechanism for a distributed MS is proposed. It enables the MS to react to changes in the available resources, operating conditions, and monitoring requirements, while maintaining high performance and low monitoring overheads. A localized decision process involving two adjacent intermediate-level managers (ILMs) and values of a local node performance parameter called temperature together determine transformations (merge, split, migrate) for each ILM. The reconfiguration mechanisms are derived reusing SNMP primitives. Interactions between MS and NCS are studied by defining a queuing model, and by evaluating different configuration schemes using simulation. Results for the static and reconfigurable schemes indicate that reconfiguration improves performance in terms of lower processing delays at the ILMs. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Monitoring

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Universal mechanisms for data-parallel architectures 36

Universal mechanisms for data-parallel architectures

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Karthikeyan Sankaralingam S.W. Keckler W.R. Mark D. Burger Computer Architecture and Technology Laboratory Department of Computer Sciences University of Texas Austin USA

ISBN: (纸本)9780769520438

Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper presents a classification scheme for data-parallel program attributes, and proposes micro-architectural mechanisms to support applications with diverse behavior for using a single reconfigurable architecture. We focus on the following four broad kinds of data-parallel programs - DSP/multimedia, scientific, networking, and real-time graphics workloads. While all of these programs exhibit high computational intensity, coarse-grain regular control behavior, and some regular memory access behavior, they show wide variance in the computation requirements, fine grain control behavior, and the frequency of other types of memory accesses. Based on this study of application attributes, this paper proposes a set of general micro-architectural mechanisms that enable a baseline architecture to be dynamically tailored to the demands of a particular application. These mechanisms provide efficient execution across a spectrum of data-parallel application and can be applied to diverse architectures ranging from vector cores to conventional superscalar cores. Our results using a baseline TRIPS processor show that the configurability of the architecture to the application demands provides harmonic mean performance improvement of 5%-55% over scalable yet less flexible architectures, and performs competitively against specialized architectures.

关键词： computer architecture Graphics Hardware Application software Computational modeling Communication system control Digital signal processing chips Engines Laboratories Reconfigurable architectures

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Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS arc...

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Annual International Symposium on computer architecture, ISCA

作者： K. Sankaralingam R. Nagarajan Haiming Liu Changkyu Kim Jaehyuk Huh D. Burger S.W. Keckler C.R. Moore Computer Architecture and Technology Laboratory Department of Computer Sciences University of Texas Austin USA

We describe the polymorphous TRIPS architecture, which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism. To adapt to small and large-grain concurrency, the TRIPS architecture contains four out-of-order, 16-wide-issue grid processor cores, which can be partitioned when easily extractable fine-grained parallelism exists. This approach to polymorphism provides better performance across a wide range of application types than an approach in which many small processors are aggregated to run workloads with irregular parallelism. Our results show that high performance can be obtained in each of the three modes-ILP, TLP, and DLP-demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.

关键词： Parallel processing computer architecture Hardware Concurrent computing Out of order Microprocessors Streaming media Process design Space technology Field programmable gate arrays

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Microprocessor pipeline energy analysis 03

Microprocessor pipeline energy analysis

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： K. Natarajan H. Hanson S.W. Keckler C.R. Moore D. Burger Department of Electrical and Computer Engineering University of Texas Austin USA Department of Computer Sciences Computer Architecture and Technology Laboratory USA

ISBN: (纸本)9781581136821

The increase in high-performance microprocessor power consumption is due in part to the large power overhead of wide-issue, highly speculative cores. Microarchitectural speculation, such as branch prediction, increases instruction throughput but carries a power burden due to wasted power for mis-speculated instructions. Pipeline over-provisioning supplies excess resources which often go unused. In this paper, we use our detailed performance and power model for an Alpha 21264 to measure both the useful energy and the wasted effort due to mis-speculation and over-provisioning. Our experiments show that flushed instructions account for approximately 6% of total energy, while over-provisioning imposes a tax of 17% on average. These results suggest opportunities for power savings and energy efficiency throughout microprocessor pipelines.

关键词： Microprocessors Pipelines Microarchitecture Circuits Energy measurement Power measurement Energy consumption Clocks Permission Hardware

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