Maintenance and evolution of complex software systems (such as large telecom embedded devices) involve activities such as reverse engineering (RE) and software visualization. Although several RE tools exist, we found ...
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Maintenance and evolution of complex software systems (such as large telecom embedded devices) involve activities such as reverse engineering (RE) and software visualization. Although several RE tools exist, we found their architecture hard to adapt to the domain specific requirements posed by our current practice in Nokia. We present an open architecture which allows easy prototyping of RE data exploration and visualization scenarios for a large range of domain models. We pay special attention to the visual and interactive requirements of the reverse engineering process. The article describes the basic architecture of our toolkit, compares it to the existing RE environments and present several visualizations taken from real cases.
The behavior of a Boltzmann Machine (BM) according to changes in the parameters that determine its convergence is experimentally analyzed to find a way to accelerate the convergence towards a solution for the given op...
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A major trend in recent cluster communication systems is to circumvent the operating system during the actual data transfers. That, on the one hand, reduces latency since there is no user-kernel transition needed and,...
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This paper compares some mntationoperators containing expert knowledge about the problem of optimizing the parameters of a Radial Basis Function Neural Network. It is shown that the expert kno wledge is not always abl...
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This paper presents the problem of optimizing a radial basis function neural network from training examples as a nulti objective problem and proposes an evolutionary algorithm to solve it properly. This algorithm inco...
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A hybrid method, based on evolutionary computation, Monte Carlo simulation, and neural networks for functional approximation and time series prediction, is proposed to reduce the high computational cost usually requir...
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This paper compares some m utationoperators containing expert knowledge about the problem of optimizing the parameters of a Radial Basis Function Neural Network. It is sho wn that the expert kno wledge is not abrays a...
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Differentiated Services (DiffServ), which are currently being standardized in the IETF DiffServ working group, is a solution that can provide different qualities of service to different network users. DiffServ aggrega...
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Soft w are visualization is an area of computer science dented to supporting the understanding and effective use of algorithms. The application of softw are visualization to Evolutionary Computation has been receiving...
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We study the space of chip multiprocessor (CMP) organizations. We compare the area and performance trade-offs for CMP implementations to determine how many processing cores future server CMPs should have, whether the ...
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We study the space of chip multiprocessor (CMP) organizations. We compare the area and performance trade-offs for CMP implementations to determine how many processing cores future server CMPs should have, whether the cores should have in-order or out-of-order issues, and how big the per-processor on-chip caches should be. We find that, contrary to some conventional wisdom, out-of-order processing cores will maximize job throughput on future CMPs. As technology shrinks, limited off-chip bandwidth will begin to curtail the number of cores that can be effective on a single die. Current projections show that the transistor/signal pin ratio will increase by a factor of 45 between 180 and 35 nanometer technologies. That disparity will force increases in per-processor cache capacities as technology shrinks, from 128KB at 100nm, to 256KB at 70nm, and to 1MB at 50 and 35nm, reducing the number of cores that would otherwise be possible.
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