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Evolutionary computation visualization: Application to G-PROP 6th

Evolutionary computation visualization: Application to G-PRO...

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6th International Conference on Parallel Problem Solving from Nature, PPSN 2000

作者： Romero, G. Arenas, M.G. Castellano, J.G. Castillo, P.A. Carpio, J. Merelo, J.J. Prieto, A. Rivas, V. Department of Architecture and Computer Technology University of Granada Campus de Puentenueva E. Granada18071 Spain Department of Computer Science University of Jaén Avda. Madrid 35 E. Jaén23071 Spain

ISBN: (纸本)9783540410560

Software visualization is an area of computer science devoted to supporting the understanding and effective use of algorithms. The application of software visualization to Evolutionary Computation has been receiving increasing attention during the last few years. In this paper we apply visualization technique to an evolutionary algorithm for multilayer perceptron training. Our goal is to better understand its internal behavior in order to improve the evolutionary part of the method. As a result of applying this this technique several deficiencies in the method have been discovered. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Evolutionary algorithms

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Clock rate versus IPC: the end of the road for conventional microarchitectures 00

Clock rate versus IPC: the end of the road for conventional ...

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Proceedings of the 27th annual international symposium on computer architecture

作者： Vikas Agarwal M. S. Hrishikesh Stephen W. Keckler Doug Burger Computer Architecture and Technology Laboratory Department of Computer Sciences The University of Texas at Austin

ISBN: (纸本)9781581132328

The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scali ng of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance—estimating both clock rate and IPC —of an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.

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Simulation of hardware support for OpenGL graphics architecture 1

Simulation of hardware support for OpenGL graphics architect...

引用

1st International Conference on Information technology: Coding and Computing, ITCC 2000

作者： Paltashev, T. Govind, N. Abla, G. Department of Electrical and Computer Engineering SD School of Mines and Technology United States Intel Corporation Computing Enhancement Architecture Lab. United States

ISBN: (纸本)0769505406

The growing number of applications for 3D graphics and imaging systems in the mass market requires the customized approach to the design of high-performance 3D graphics and imaging system architectures. That fact coupled with the strong trends to industrial standardization of graphics API, such as OpenGL, leads to enhanced portability for imaging and graphics applications. The progress on the hardware support of API functionality gives a real possibility to use a top-down approach in the design of custom graphics/imaging systems based on the mixed hardware/software implementation of the OpenGL architecture. Software simulation is a relatively cheap and fast way for initial graphics architecture template development and evaluation to acquire the structure and parameters that can be used later for HDL elaboration and simulation. This paper discusses a 3D graphics and imaging system architecture model implementation based on OpenGL API hardware support simulation. The object-oriented approach has been used for this development of analytic and software models simulating hardware units on different stages of the graphics pipeline. The Interactive Imaging System architecture Composer has been developed in this project for fast run-time simulation management, data acquisition and interpretation. The expandable set of architecture templates uses a reconfigurable shared library of "virtual hardware units" simulating the different hardware structures for graphics and image processing. © 2000 IEEE.

关键词： Imaging systems

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A network-computing infrastructure for tool experimentation applied to computer architecture education

A network-computing infrastructure for tool experimentation ...

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2000 Workshop on computer architecture Education, WCAE 2000

作者： Figueiredo, Renato J. Fortes, José A. B. Eigenmann, Rudolf Kapadia, Nirav Adabala, Sumalatha Miguel-Alonso, Jose Taylor, Valerie Livny, Miron Vidal, Luis Chen, Jan-Jo School of ECE Purdue University United States Department of EECS Northwestern University United States Dept. of Mathematics and Computer Science Chicago State University United States Dept. of Computer Architecture and Technology University of the Basque Country Spain Computer Sciences Department University of Wisconsin-Madison United States

ISBN: (纸本)9781450347303

computer architects increasingly depend on the use of software tools to evaluate and investigate the design of computer systems. It is therefore very important that educators in this field promote extensive tool-based student experimentation in architecture classes. However, the integration of today's complex architecture tools into curricula poses several challenges to an instructor, including management of powerful computing resources, software installation and maintenance, and development of tool-specific educational material. This paper describes how these challenges are addressed by a universally accessible network-computing infrastructure - NETCARE - that provides educators with a Web portal to access computing resources, executable tools and educational material. Copyright held by author.

关键词： Portals

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A new radial basis function networks structure: application to time series prediction

A new radial basis function networks structure: application ...

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International Joint Conference on Neural Networks (IJCNN)

作者： I. Rojas H. Pomares J. Gonzalez E. Ros M. Salmeron J. Ortega A. Prieto Department of Architecture and Computer Technology University of Granada Spain

Describes a structure to create a RBF neural network. This structure has 4 main characteristics. The first one is that the special RBF network architecture uses regression weights to replace the constant weights normally used. These regression weights are assumed to be functions of input variables. The second characteristic is the normalization of the activation of the hidden neurons (weighted average) before aggregating the activations, which, as observed by various authors, produces better results than the classical weighted sum architecture. The third aspect is that a new type of nonlinear function is proposed, the pseudo-gaussian function (PGBF). With this, the neural system gains flexibility, as the neurons possess an activation field that does not necessarily have to be symmetric with respect to the centre or to the location of the neuron in the input space. In addition to this new structure, we propose, as the fourth and final feature, a sequential learning algorithm, which is able to adapt the structure of the network, with this, it is possible to create new hidden units and also to detect and remove inactive units.

关键词： Radial basis function networks Neurons Neural networks Application software computer architecture Input variables Function approximation computer networks Technological innovation

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What are the main functional blocks involved in the design of adaptive neuro-fuzzy inference systems?

What are the main functional blocks involved in the design o...

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International Joint Conference on Neural Networks (IJCNN)

作者： I. Rojas J.L. Bernier R. Rodriguez-Alvarez Z. Prieto Department of Architecture and Computer Technology University of Granada Spain

Because there are many possibilities for the set of basic functions, parameters and operators used in the design of an adaptive-network-based fuzzy inference system (ANFTS), the search for the most suitable operators and functional blocks, together with their characterization and evaluation, is also an important topic in the field of neuro-fuzzy design. As shown in papers dealing with real applications, the designer has to select the operator to be used in each phase in the design of a neuro-fuzzy system, and this decision is usually taken in terms of the most common operations performed. Nevertheless, it is very important to determine which factors have the greatest influence on the behaviour and performance of the neuro-fuzzy system. Therefore, the designer should pay close attention to the phase in which the selection of the operator is most statistically significant. In this way, it is possible to obviate a detailed analysis of different configurations that lead to systems with very similar performance. In order to perform this analysis, an appropriate statistical tool has been used: the multifactorial analysis of the variance (ANOVA) which consists of a set of statistical techniques that enable the analysis and comparison of experiments, by describing the interactions and interrelations between either the quantitative or the qualitative variables of the neural network system. By applying this methodology to a great variety of neuro-fuzzy systems, it is possible to obtain general results about the most relevant factors defining the neural network design.

关键词： Adaptive systems Fuzzy systems Analysis of variance Fuzzy neural networks Performance analysis Neural networks Network topology Fuzzy sets Programmable control Adaptive control

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Clock rate versus IPC: the end of the road for conventional microarchitectures

Clock rate versus IPC: the end of the road for conventional ...

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Annual International Symposium on computer architecture, ISCA

作者： V. Agarwal M.S. Hrishikesh S.W. Keckler D. Burger Computer Architecture and Technology Laboratory Department of Computer Sciences University of Texas Austin Austin TX USA

The doubling microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor dock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance-estimating both clock rate and IPC-of an aggressive out-of-order microarchitecture as it is scaled from a 250 nm technology to a 35 nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5% which is far worse than the annual 50-60% to which we have grown accustomed.

关键词： Clocks Roads Microarchitecture Wire Delay Microprocessors Transistors Semiconductor devices Capacitance Performance evaluation

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Simulation of hardware support for OpenGL graphics architecture

Simulation of hardware support for OpenGL graphics architect...

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International Conference on Information technology: Coding and Computing (ITCC)

作者： T. Paltashev N. Govind G. Abla Department of Electrical and Computer Engineering SD School of Mines and Technology Computing Enhancement Architecture Laboratory Intel Corporation

关键词： Graphics Object oriented modeling computer architecture Standardization Application software Hardware design languages Analytical models Pipelines Runtime Project management

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Nomadic routing applications for wireless networking in a team of miniature robots

Nomadic routing applications for wireless networking in a te...

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IEEE International Conference on Systems, Man and Cybernetics

作者： J. Budenske J. Bonney A. Ahamad R. Ramanujan D.F. Hougen N. Papanikolopoulos Department of Computer Science and Engineering University of Minnesota Minneapolis MN USA Architecture Technology Corporation Eden Prairie MN USA

Distributed robotics uses multiple robots through coordination of task to solve problems. Developing a distributed robotic system introduces a number of challenges, one of which is the intra-robot communication and networking of data and commands. Due to the characteristics of the targeted robotic missions and environments, the wireless networking requirements impose stringent constraints in terms of available memory, processing, and power consumption. Designing under these constraints and still providing support for such functions as synchronous commands and proxy processing is the true challenge. This paper discusses research in providing a lightweight wireless routing/networking solution that can dynamically tune the intra-robotic networking to adapt to the robotic team's mission needs and the environment situation encountered.

关键词： Routing Intelligent networks Robot kinematics Robot sensing systems Orbital robotics Remotely operated vehicles Mobile robots Military computing Energy consumption Communication system security

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Industrial evaluation of DRAM SIMM tests

Industrial evaluation of DRAM SIMM tests

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IEEE International Test Conference

作者： Ad.J. van de Goor A. Paalvast Faculty of Information Technology and Systems Department of Electrical Engineering Section Computer Architecture and Digital Technique Delft University of Technnology Delft Netherlands

This paper describes the results of testing 50 single inline memory modules (SIMMs) each containing 16 16 Mbit DRAM chips (DUTs); 39 SIMMs failed, and of the 800 DUTs, 116 failed. In total 54 different test algorithms have been applied, using up to 168 different stress combinations for each test. The results show that GAL9R is the best test. Furthermore, it is shown that burst mode tests detect a completely different class of faults as compared with traditional word mode tests, and that tests with address scrambling enabled the detection of more faults.

关键词： Random access memory Stress Fault detection Production Performance evaluation Information technology computer architecture Electronic mail System testing Manuals

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