This paper proposes a continuous, non-invasive blood pressure monitoring system concept, which uses a safety microprocessor to connect sensors for building a body sensor network. The changes in Pulse Transit Time (PTT...
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(纸本)9781467347358
This paper proposes a continuous, non-invasive blood pressure monitoring system concept, which uses a safety microprocessor to connect sensors for building a body sensor network. The changes in Pulse Transit Time (PTT) can be detected with the sensor network. The microprocessor gathers the PTT and other vital signs of the patient to derive changes in blood pressure. Through the new Bluetooth protocol for safety systems, the current blood pressure value can be sent to a variety of terminals present in the wireless network, such as mobile phone, PC and medical monitoring systems. The 1oo2 architecture of the used microprocessor can provide high safety to a rating of safety integrity level 3 (SIL3), thus the whole network can meet the safety required in medical care systems.
Sensor communication applications not only require high performance processing but also flexible and reliable computing. Today, standard microprocessor systems are still application oriented and aren't suitable by...
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Sensor communication applications not only require high performance processing but also flexible and reliable computing. Today, standard microprocessor systems are still application oriented and aren't suitable by implication for reliability-related and safety-related applications. In order to achieve a certain safety integrity level (SIL), several measures, methodologies and especially additional components should be considered, which leads to more and more complex systems. For this reason, new application devices should be targeted. In this context, reconfigurable devices such as SRAM-based Field Programmable Gates Arrays (FPGAs) provide a suitable solution due to their flexibility, and the necessary computing performance at affordable design cost and time. In fact, SRAM-Based FPGAs are nowadays frequently used in embedded communication systems due to their design flexibility and reconfigurability. This paper presents a prototyping platform for an FPGA-based safety-related communication system for a wireless sensor network. As a case study an acceleration sensor application is introduced.
Wireless sensor networks for monitoring and steering industrial systems have emerged as an important new application area for wireless embedded technology in safety-related systems. Therefore several hardware platform...
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Wireless sensor networks for monitoring and steering industrial systems have emerged as an important new application area for wireless embedded technology in safety-related systems. Therefore several hardware platforms can be targeted. Due to their flexibility and reconfigurability along with high performance and power efficiency, modern Field Programmable Gate Arrays (FPGAs) are an excellent platform to realize such intelligent sensor networks. On one hand, FPGAs can integrate embedded processors and on-chip memory into a single die and can be easily configured to interface with a wide variety of popular communications protocols like SPI, UART and I2C, which are used for sensor communication. On the other hand, the reconfigurability of FPGAs supports the design of self-organizing computing systems, which are increasingly used in sensor applications. In this paper an FPGA-based wireless smart sensor network that integrates acceleration sensors for increasing safety aspects in cognitive systems used for industrial communication is presented.
With the announcement and development of safety standards such as IEC 61508 and DO-254 standards a basis for the implementation of qualitative and quantitative analyzes in the areas of reliability and safety for elect...
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With the announcement and development of safety standards such as IEC 61508 and DO-254 standards a basis for the implementation of qualitative and quantitative analyzes in the areas of reliability and safety for electronic safety-related systems was laid. Especially with the publication of the second edition of the standard IEC 61508 standard and the introduction of new aspects such as on-chip redundancy and the use of integrated systems in such systems is becoming increasingly attractive. SRAM-based FPGAs are considered as the mainstream FPGA technology and represent an excellent platform for the development of system-on-chips due to their complexity and programming flexibility. In this paper, the implementation of FPGA-based safety-related systems according to the standard IEC 61508 is targeted. First, the advantages and challenges of FPGAs for the use in such systems are presented. Afterwards, measures and methodologies are discussed, which are required for the implementation of such systems. Finally suitable FPGA implementation of these measures is presented.
This paper presents a new method by which it is possible to realistically predict the software reliability of critical systems. The main feature of this method is that it allows estimating the number of remaining crit...
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This paper presents a new method by which it is possible to realistically predict the software reliability of critical systems. The main feature of this method is that it allows estimating the number of remaining critical faults in the software. The algorithm employs well-known methods such as Imperfect Debugging and it provides a more reliable prognosis than the methods conventionally used for this purpose. Furthermore, the new approach describes two processes of handling critical failures (one for detection and one for correction). The new algorithm also takes into account the socalled repair time, a measurement that is vitally important for a reliable prognosis. For use in the prediction model, it is mathematically described as a time function. As every programmer knows, it can be difficult to have even the simplest program run without faults. So-called software reliability models (SRM's), based on stochastic and aiming to predict the reliability of both software and hardware, have been used since the 70's. SRM's rely on certain model assumptions some of which cannot be deemed realistic anymore. Hence, for today's reliability engineering, these models are insufficient. At this point in time, though, there are hardly any methods that enable us to obtain predictions as to how the reliability of critical faults or the failure rate of critical systems behave over time. Currently, there is no mathematical model distinguishing between critical and non-critical faults, and only few models consider Imperfect Debugging (ID). The method presented here, however, is based on ID and it is able to distinguish between critical and non-critical software faults. Moreover, this new method employs a so-called Time-Delay and thus two new processes have to be designed. Mathematically, these processes describe the detection of faults and their correction, respectively. It is necessary to define appropriate distribution functions and to clearly state the requisite model assumptions.
In order to measure the effectiveness of safety protection systems there are several design parameters. Diagnostic coverage factor is one of the most important parameter which influences all architectures. In this sho...
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High reliability and high availability are essential aspects for all critical elements used in automotive applications. This is particularly true for control and steering systems. In this regard, numerous steer by wir...
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High reliability and high availability are essential aspects for all critical elements used in automotive applications. This is particularly true for control and steering systems. In this regard, numerous steer by wire (x-by-wire) concepts were developed over the years. Most of them considered only standard single microcontroller systemarchitectures with a low degree of reliability according to international reliability and safety standards. This paper presents a novel concept for a degradable safety controller for steer-by-wire systems. Based on a safety-related 1004-architecture, the presented concept offers higher safety, reliability and availability.
This paper is concerned with the design procedures of an automated testing tool, developed in Matlab®/Simulink® environment, that performs software verification during runtime on a PLC (Programmable Logic Co...
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Due to the complexity of microprocessor, an efficient testing is a crucial point and serious challenge in safety systems. A new instruction opcode for ALU based Built-In-Test (BIT) is proposed in this paper. With this...
Due to the complexity of microprocessor, an efficient testing is a crucial point and serious challenge in safety systems. A new instruction opcode for ALU based Built-In-Test (BIT) is proposed in this paper. With this novel method stuck-at-fault in Multiplexer (MUX) for Arithmetic Logic Unit (ALU) can be determined. A model that consists of the command and faulty states is developed. According to the designed state model, an algorithm and pseudo program that tests the stuck-at-fault in MUX is implemented and described in this paper.
In order to use electronic systems comprising of software and hardware components in safety related and high safety related applications, it is necessary to meet the Marginal risk numbers required by standards and leg...
In order to use electronic systems comprising of software and hardware components in safety related and high safety related applications, it is necessary to meet the Marginal risk numbers required by standards and legislative provisions. Existing processes and mathematical models are used to verify the risk numbers. On the hardware side, various accepted mathematical models, processes, and methods exist to provide the required proof. To this day, however, there are no closed models or mathematical procedures known that allow for a dependable prediction of software reliability. This work presents a method that makes a prognosis on the residual critical error number in software. Conventional models lack this ability and right now, there are no methods that forecast critical errors. The new method will show that an estimate of the residual error number of critical errors in software systems is possible by using a combination of prediction models, a ratio of critical errors, and the total error number. Subsequently, the critical expected value-function at any point in time can be derived from the new solution method, provided the detection rate has been calculated using an appropriate estimation method. Also, the presented method makes it possible to make an estimate on the critical failure rate. The approach is modelled on a real process and therefore describes two essential processes - detection and correction process.
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