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1992 IEEE INTERNATIONAL SYMP ON INTELLIGENT CONTROL

作者： KLOMP, C MULLER, FL REGTIEN, PPL Delft University of Technology Department of Electrical Engineering Control Laboratory i Computer Architecture i Electronic Instrumentation P.O. Box 5031 Delft 2600 GA Netherlands

ISBN: (纸本)0780305469

The usage of a tactile image sensor for acquiring additional information about assembly tasks (or other fine motion tasks) is proposed. The sensor used is based on the piezoresistivity of a conductive polymer film (FSR). It contains 16x16 taxels (tactile elements) over an area of 4x4 cm. In order to minimize the time needed to transfer the data to the robot controller and to process the data in the robot controller, a preprocessing unit for the tactile. data is being developed. The unit must be able to detect and recognize objects, extract the position and orientation of an object and detect slip. Scanning the complete image is too time consuming, therefore only the contour points of an object will be scanned, thereafter the vertices of the contour are detected. The last step consists of matching these vertices with the vertices of the objects in the database. Sample objects have been used to show the results of the vertex detection in hardware. The data of the preprocessing unit will be used in several ways by the robot controller. The object recognition feature is used for grasp verification, after which the position of the object relative to the gripper can be used to adjust the robot position. Slip detection is used in real time as an indication of errors while performing assembly operations. During these operations the robot will be controlled, based on force and position information (active compliance). The implementation of the proposed algorithms will be performed with transputer based hardware, which is currently being developed. Tests with a prototype board of the hardware have shown that the desired sample rates (S lms) can easily be obtained. © 1992 IEEE.

关键词： Polymer films

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IDRIS - INTERACTIVE DESIGN OF REACTIVE INFORMATION-SYSTEMS 4th

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4TH INTERNATIONAL CONF ON ADVANCED INFORMATION SYSTEMS ENGINEERING ( CAISE 92 )

作者： OSMON, P SLEAT, P Systems Architecture Research Centre Computer Science Department City University London EC 1V 0HB United Kingdom Marex Technology Ltd Marex House 88 The High Street Cowes I.O.W. United Kingdom

ISBN: (纸本)3540554815

The IDRIS project is developing a model, a methodology, a notation, and a CASE tool for the interactive design of real-time, or reactive, systems. Increasingly such designs are implemented on parallel hardware, for performance and reliability reasons. The work described here addresses performance, but not reliability, issues. The model describes a real time system in terms of a database and a set of asynchronous tasks. Each task is the system's response to an external stimulus event. A task decomposes into atomic transactions, acting on entities in the database, connected by a control structure which is determined by entity access constraints. Based on a static analysis of these data dependencies, the methodology is able to rely on scheduling rather than conventional locking to control access to the database. The model describes real time systems generally. The methodology concentrates on the class of hard real time systems designs — those which must guarantee to meet the response latency and throughput constraints specified by the requirements. The methodology uses scheduling and allocation heuristics to map tasks and their transactions onto physical processors. The methodology has a number of stages and the designer is assisted by four graphical notations: event context diagrams;data dependency rings for capturing both intra task and inter task data dependencies;precedence graphs for expressing the intra task control structure implied by the data dependencies;Gantt charts for expressing worst case schedules. The methodology assumes a run time environment with a hierarchy of schedulers to control processing and access to data entities. An interactive CASE tool helps the designer capture and manipulate the design information, display partial designs, and perform allocation and scheduling trials against the specification. An example real time system design, for a ship control system, generated using the methodology and the CASE tool, is briefly described. © Springer-

关键词： Scheduling

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IMPROVING THE SHIP DESIGN, ACQUISITION AND CONSTRUCTION PROCESS

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NAVAL ENGINEERS JOURNAL 1992年第2期104卷 39-57页

作者： RYAN, JC JONS, OP J. Christopher Ryan:earned his bachelor's and master's degrees in Naval Architecture from Webb Institute and MIT respectively. He spent three years at the Advanced Marine Technology Division of Litton Industries working on the DD-963 class ship design and related computer aided design projects. he subsequently went to the Navy Department concentrating on early stage design of surface combatants for 12 years including work on the FFG-7 Sea Control Ship CSGN and CVV aircraft carrier projects. He then shifted focus and became the technical director for the Computer Supported Design Program in NavSea for five years. Mr. Ryan has served in several supervisory positions within the Ship Design Group in NavSea since that time. He is currently the project manager for the Ship Design Acquisition and Construction Process Improvement Project. Otto P. Jons:received a Diplom Ing. in shipbuilding from the Technical University of Hannover W. Germany and an M.S. in naval architecture and marine engineering from the Massachusetts Institute of Technology in 1967. He then joined Litton Ship Systems where he was responsible for the preliminary design of the DD-963 hull structure and then for ship systems as manager LHA Ship Systems Engineering Department. From 1972 to 1974 he was principal research scientist at Hydronautics. In 1976 as technical director he helped establish the local office of Designers and Planners. Otto Jons was one of the co-founders of Advanced Marine Enterprises Inc. in 1976 where he is corporate vice president engineering.

In the spring of 1990, the NavSea Chief Engineer initiated a project to improve the design, acquisition and construction (DAC) of U.S. Navy ships. The project's objectives are to reduce the time and cost of acquiring and operating Navy ships while improving their quality, unlike previous studies on the subject, the project utilizes a rigorous process analysis approach and attempts to use quantitative measures as the basis for recommending improvements. The paper is, of necessity, a status report on the progress of this project. Topics covered include: the DAC process;a look at the current state of ship acquisition time, cost, and quality;the methodology for process improvements;and early findings.

关键词： Naval Vessels

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THE USE OF PROPULSION SHAFT TORQUE AND SPEED MEASUREMENTS TO IMPROVE THE LIFE-CYCLE PERFORMANCE OF UNITED-STATES NAVAL SHIPS

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NAVAL ENGINEERS JOURNAL 1992年第6期104卷 43-57页

作者： HUNDLEY, LL TSAI, SJ Lowry L. Hundley:is a project manager/instrumentation engineer with the Hydromechanics Department at the Carderock Division Naval Surface Warfare Center. His 25 years of experience include the planning and directing of sea trials on Navy Coast Guard and commercial ships. Mr. Hundley has been responsible for assessing and improving the methods used to collect and analyze ship powering and maneuvering data. He received a B.S. degree in electrical engineering from Virginia Polytechnic Institute in 1967 and is a member of ASNE. Shou-Jen Tsai:is a naval architect with the Full-Scale Trials Branch Ship Hydromechanics Department at Carderock Division Naval Surface Warfare Center. His 20 years of experience include ship repair and computer-aided ship design and performance analysis. He is a licensed marine engineer with 5 years of shipboard operation experience. Mr. Tsai received a B.S. degree in naval architecture from Taiwan Provincial College of Marine and Oceanic Technology in 1970 and a master's degree in ocean engineering from Stevens Institute of Technology in 1980.

This paper describes the benefits of having permanent torsionmeters installed on the main propulsion shafting of U. S. naval ships. Propulsion shaft torque and speed measurements provide ship operators with accurate knowledge of the ship's powering condition at any given time. This information can be compared with baseline data to reveal degradation in the ship's powering performance. Performance trends produced by observations over an extended period of time can be utilized to forecast the point at which corrective action should be taken. The timely implementation of necessary corrective action can significantly decrease the ship's operating cost by reducing fuel consumption while minimizing excessive wear on the ship's machinery and, in all probability, extend the ship's service life. The value of accurate powering measurements is discussed in conjunction with (1) the accumulation and removal of hull and propeller marine growth, (2) single shaft operation, and (3) ships equipped with controllable pitch propellers. An overview of modern torsionmeters is presented based on literally hundreds of sea trials involving personnel from the Carderock Division. Naval Surface Warfare Center. Development of an overall program is suggested to ensure that (1) only accurate and reliable torsionmeters are installed on U. S. naval ships, (2) the meters are properly maintained and monitored, and (3) full utilization is made of the data obtained and of the baseline data currently available.

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Software pipelining for transport-triggered architectures 24

Software pipelining for transport-triggered architectures

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Proceedings of the 24th International Symposium on Microarchitecture - MICRO 24

作者： Hoogerbrugge, Jan Corporaal, Henk Mulder, Hans Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems

ISBN: (纸本)0897914600

This paper discusses software pipelining for a new class of architectures that we call transport-triggered. These architectures reduce the interconnection requirements between function units. They also exhibit code scheduling possibilities which are not available in traditional operation-triggered architectures. In addition the scheduling freedom is extended by the use of so-called hybridpipelined function utits. In order to exploit this tleedom, existing scheduling techniques need to be extended. We present a software pipelirtirtg technique, based on Lam's algorithm, which exploits the potential of !mnsport-triggered architectures. Performance results are presented for several benchmak loops. Depending on the available transport capacity, MFLOP rates may increase significantly as compared to scheduling without the extra degrees of freedom. © 1991 ACM.

关键词： Scheduling

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An implementation of a barotropic numerical weather prediction model in the functional language SISAL 90

An implementation of a barotropic numerical weather predicti...

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2nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 1990

作者： Chang, Pau S. Egan, Gregory K. Jt. Roy. Melbourne Inst. of Technol. and Cmw. Scientific and Industrial Research Organisation Parallel Systems Architecture Project Australia Royal Melbourne Institute of Technology Dept of Communication and Electrical Engineering 124 La Trobe St. Melbourne3000 Australia Department of Computer Systems Engineering Swinburne Institute of Technology School of Electrical Engineering John Street Hawthorn3122 Australia

ISBN: (纸本)0897913507

Numerical Weather Prediction (NWP) is acknowledged as being of vital importance to economy. The demand that NWP places on computing system performance has increased dramatically since the introduction of computer systems and is siili growing. This paper describes the implementation of a one-level barotropic spectral NWP model using the high level functional language SISAL. Our initial approach was a direct transliteration from FORTRAN to SISAL, the result of which was a large amount of array copying and loss of parallelism. The algorithm of the model was then rearranged to enable effective exploitation of parallelism by an optimising SISAL compiler. The parallel implementation technique and its potential for modeling with larger model sizes are discussed, and the improved results for an Encore Multimax multiprocessor are presented. © 1990 ACM.

关键词： High level languages

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computer-SYSTEM architecture CONCEPTS FOR FUTURE COMBAT SYSTEMS

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 43-62页

作者： ZITZMAN, LH FALATKO, SM PAPACH, JL Dr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin

This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computer systems architecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computer systems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat. Changes to the current Aegis computer architecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computer architecture to a general architecture for the future. The proposed computer systems architecture concepts encompass the use of combinations of physically distributed, microprocessor-based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi-warfare tactical picture supporting the future combatant command st

关键词： computer architecture

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COMPARATIVE STRUCTURAL LIFE ASSESSMENT OF PATROL BOAT BOTTOM PLATING

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 253-262页

作者： AYYUB, BM WHITE, GJ BELLWRIGHT, TF PURCELL, ES Bilal M. Ayyub:is currently an associate professor of civil engineering at the University of Maryland. He received his B.S. degree in civil engineering from the University of Kuwait in 1980. He completed both his M.S. (1981) and Ph.D. (1983) in civil engineering at the Georgia Institute of Technology. Dr. Ayyub has an extensive background in risk-based analysis. He is engaged in research work involving structural reliability marine structures and mathematical modeling using the theories of probability statistics and fuzzy sets. His research work has been sponsored by the National Transportation Safety Board National Science Foundation U.S. Coast Guard Department of Defense State of Maryland and University of Maryland. He is the author of more than 100 publications in national and international journals conference proceedings and reports. Dr. Ayyub was a recipient of the ASNE “Jimmie” Hamilton Award for 1985 the ASCE “Outstanding Research Oriented Paper” in theJournal of Water Resources Planning and Managementfor 1987 and Edmund Friedman Young Engineer Award for Professional Achievement from ASCE for 1989. Gregory J. White:is an associate professor of naval architecture at the U.S. Naval Academy. He received his B.S. degreein engineering mechanics from Vanderbilt University in 1975 an M.E. degree in naval architecture from the University of California Berkeley in 1981 and a Ph.D. in civil engineering (structures) from the University of Maryland in 1986. Dr. White served on active duty with the U.S. Navy from 1975 to 1979 as a junior officer in the engineering and operations departments of Pacific Fleet destroyers. Prior to coming to the Naval Academy he worked at Mare Island Naval Shipyard in the scientific code and in the R&D division of Exxon International company's Tanker Department. Dr. White is the author of more than two dozen technical articles and reports and is one of the U.S. representatives to the International Ship and Offshore Structures Congress (ISSC). His research interests lie in t

The estimation of an absolute life expectancy of a structure is a complex process and the results are expected to have relatively large levels of uncertainty. In this study, a comparative analysis is undertaken between two different patrol boats. This is an approach which results in a higher confidence level because certain factors common to both boats can be eliminated by assuming them to be at constant normal levels. The study is limited to the critical forward bottom plating and takes into account the differences in material, plate dimensions, operational profile, structure and loading of the two vessels. Two failure modes, plastic plate deformation and fatigue, are considered, and a novel approach to plate wastage is included. Many factors affect the structural life of a vessel. They include structural type, operational profile, structural details, loads, inspection and maintenance, design methods, safety factors, corrosion, and environmental factors. There are three types of uncertainty associated with these factors; namely, physical randomness, statistical uncertainties, and model uncertainties. The method described is designed to address these uncertainties. The objective of the paper is to present the reliability-based structural life assessment method, and then to use it to evaluate and compare the structural performance of the forward bottom plating of the two patrol boats. The results of the evaluation are presented in the form of graphs and tables in order to facilitate the comparative evaluation. The method is performed within a computer-based format which allows parametric sensitivity analysis of several variables including the size of the plating panel, thickness, operational profile and loading. The sensitivity of the structural life expectancy of the forward bottom plating to variations in these parameters is evaluated.

关键词： Naval Vessels

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A Necessary and Sufficient Condition for the Total Unimodularity of a Matrix in Terms of Graph Theory

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Optimization 1989年第6期20卷 901-914页

作者： Hempel, L. Herrmann, U. Hölzer, W. Wetzel, R. Weimar College of Architecture and Civil Engineering Department of Computer Science and Mathematics Germany Leipzig Institute of Technology Department of Mathematics and Computer Science Germany

We present a necessary and sufficient condition for an arbitrary matrix A to be totally unimodular. The matrix A is interpreted as the adjacency matrix of a bipartite graph G(A). The total unimodularity of A corresponds to non-existence of a cycle in G(A) which has an odd columnvaluation and which is equal to the induced subgraph. Some applications of the results are also discussed. © 1989, Taylor & Francis Group, LLC. All rights reserved.

关键词： Bipartite graphs Multicommodity flow Perfect matching Total unimodularity

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Data buffering: run-time versus compile-time support

Data buffering: run-time versus compile-time support

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Third International Conference on Architectural Support for Programming Languages and Operating Systems Architectural Support for Programming Languages and Operating Systems

作者： Mulder, Hans Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology PO Box 5031 2600 AG Delft The Netherlands

ISBN: (纸本)0897913000

Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).A utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. This paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). This paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. It shows the utility increase of applying register allocation for multiple register sets. The paper also shows a potential utility decrease inherent to stack buffers. The observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion

关键词： computer operating systems

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