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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Mulder, Hans Stravers, Paul Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands

ISBN: (纸本)0897913248

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture. The SCalable architecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures;tools for synthesizing architectures from application or application-area;VLSI cell libraries and tools for quick generation of application-specific processors;a system-software platform which can be retargeted quickly to fit the application-specific architecture;This paper concentrates on the micro-architecture framework of SCARCE and outlines the process of generating VLSI processors. © 1990 ACM.

关键词： Cost effectiveness

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Cost-effective design of application specific VLIW processors using the SCARCE framework 22

Cost-effective design of application specific VLIW processor...

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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Mulder, Hans Portier, Robert J. Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands

ISBN: (纸本)0897913248

Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs;especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these costs to be reduced, but the flexibility often reduces efficiency. VLIW is a new and promising concept for the design of low-cost, high-performance parallel computer systems. We suggest that the VLIW concept can also be used as a basis for cost-effective design of application-specific processors which must exploit application-resident parallelism. The SCARCE (SCalable architecture Experiment) framework, an approach for cost-effective design of application-specific processors, provides features which allow the design of retargetable VLIW architectures. However, a retargetable VLIW architecture is only effective if there is a retargetable VLIW compiler. Since a VLIW compiler is an essential part of the VLIW architecture, tradeoffs must be made between the variety of VLIW architectures and the compiler complexity. We suggest that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space. This paper discusses the issues related to the design of a retargetable VLIW processor architecture and compiler within the SCARCE framework. © 1990 ACM.

关键词： Very long instruction word architecture

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An architecture framework for application-specific and scalable architectures 89

An architecture framework for application-specific and scala...

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Proceedings of the 16th annual international symposium on computer architecture

作者： J. M. Mulder R. J. Portier A. Srivastava R. in't Velt Section Digital Systelns and Computer Architecture Department of Electrical Engineering Delft University of Technology POBox 5031260O AG Delft The Netherlands

ISBN: (纸本)9780897913195

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each *** SCalable architecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture;This paper concentrates primarily on the architecture framework of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.

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Preface

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 1989年 366 LNCS卷 V-IV页

作者： Odijk, Eddy A. M. Rein, Martin Syre, Jean-Claude Philips Research Laboratories Computer Architecture P.O. Box 80.000 Eindhoven5600 JA Netherlands Department of Computer Science Eindhoven University of Technology P O. Box 513 Eindhoven5600 MB Netherlands ECRC European Computer Industry Research Centre Computer Architecture Arabellastr. 17 München 81D-8000 Germany

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Preface

Lecture Notes in Computer Science (including subseries Lectu...

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 1989年 365 LNCS卷 III-IV页

作者： Odijk, Eddy A. M. Rem, Martin Syre, Jean-Claude Philips Research Laboratories Computer Architecture P.O. Box 80.000 Eindhoven5600 JA Netherlands Department of Computing Science Eindhoven University of Technology PO. Box 513 Eindhoven5600 MB Netherlands ECRC European Computer Industry Research Centre Computer Architecture Arabellastr. 17 München 81D-8000 Germany

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THE QUANTIFICATION OF INTEROPERABILITY

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NAVAL ENGINEERS JOURNAL 1989年第3期101卷 251-256页

作者： MENSH, DR KITE, RS DARBY, PH Dennis Roy Mensh:is currently the task leader Interoperability Project with the MITRE Corporation in McLean Va. He received his B.S. and M.S. degrees in applied physics from Loyola College in Baltimore Md. and the American University in Washington D. C. He also has completed his course work towards his Ph.D. degree in computer science specializing in the fields of systems analysis and computer simulation. He has been employed by the Naval Surface Warfare Center White Oak Laboratory Silver Spring Md. for 20 years in the areas of weapon system analysis and the development of weapon systems simulations. Since 1978 he has been involved in the development of tools and methodologies that can be applied to the solution of shipboard combat system/battle force system architecture and engineering problems. Mr. Mensh is a member of ASNE MORS IEEE U.S. Naval Institute MAA and the Sigma Xi Research Society. Robert S. Kite:is a systems engineer with the Naval Warfare Systems Engineering Department of the MITRE Corporation in McLean Va. Mr. Kite received his B.S. degree in electronic engineering from The Johns Hopkins University in Baltimore Md. Mr. Kite retired from the Federal Communications Commission in 1979 and served a project manager of the J-12 Frequency Management Support Project for the Illinois Institute of Technology Research Institute in Annapolis Md. before joining MITRE. Mr. Kite is presently a member of ASNE the Military Operations Research Society and an associate member of Sigma Xi. Paul H. Darby:has worked in the field of interoperability both in the development of interoperability concepts and systems since joining the Department of the Navy in 1967. He was the Navy's program manager for the WestPacNorth TACS/ TADS and IFFN systems. He is currently head of the Interoperability Branch Warfare Systems Engineering Office Space and Naval Warfare Systems Command. He holds a B.S. from the U.S. Naval Academy.

JCS Pub 1 defines interoperability as “The ability of systems, units or forces to provide services to and accept services from other systems, units or forces and to use the services so exchanged to enable them to operate effectively together.” With JCS Pub 1 as a foundation, interoperability of systems, units or forces can be factored into a set of components that can quantify interoperability. These components are: media, languages, standards, requirements, environment, procedures, and human factors. The concept described in this paper uses these components as an analysis tool to enable specific detailed analyses of the interoperability of BFC3 systems, units, or forces for the purpose of uncovering and resolving interoperability issues and problems in the U.S. Navy, Joint, and Allied arenas. Also, as a management tool, the components can help determine potential interoperability characteristics of future U.S. Navy BFC3 systems for compliance with battle force systems architectures. The approach selected for the quantification of interoperability was the development of a set of measures of performance (MOPs) and measures of effectiveness (MOEs). The MOPs/MOEs were integrated with a candidate set of components, which were used to partition the totality of interoperability into measurable entities. The methodology described employs basic truth table theory in conjunction with logic equations to evaluate the interoperability components in terms of MOPs that were aggregated to MOEs. It is believed that this concept, although elementary and based on fundamental principles, represents an operationally significant approach rather than a theoretical approach to the quantification of interoperability. The vehicle used as a means to measure the MOPs and MOEs was the Research Evaluation and Systems Analysis (RESA) computer modeling and simulation capability at the Naval Ocean Systems Center (NOSC), San Diego, Calif. Data for the measurements were collected during a Tactical I

关键词： Military Engineering

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ESTIMATION OF STRUCTURAL SERVICE LIFE OF SHIPS

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NAVAL ENGINEERS JOURNAL 1989年第3期101卷 156-166页

作者： AYYUB, BM WHITE, GJ PURCELL, ES P.E. Bilal M. Ayyub:is currently an associate professor of civil engineering at the University of Maryland. He received his B.S. degree in civil engineering from the University of Kuwait in 1980. He completed both his M.S. (1981) and Ph.D. (1983) in civil engineering at the Georgia Institute of Technology. Dr. Ayyub has an extensive background in risk-based analysis and design simulation and construction engineering. He is engaged in research work involving structural reliability bridges marine structures and mathematical modeling using the theories of probability statistics and fuzzy sets. His research work is sponsored by the National Transportation Safety Board the National Science Foundation the U.S. Coast Guard the State of Maryland and the University of Maryland. Dr. Ayyub is a member of ASNE the American Society of Civil Engineers (ASCE) the American Concrete Institute (ACI) the Committee on Forensic Engineering of ASCE and the Committee on Structural Safety of ACI. He is the author of more than three dozen publications in national and international journals conference proceedings and reports. Dr. Ayyub received the ASNE “Jimmie” Hamilton Award for 1985 and the ASCE “Outstanding Research Oriented Paper” in the Journal of Water Resources Planning and Management for 1987. Gregory J. White:is an associate professor of naval architecture at the U.S. Naval Academy. He received his B.S. degree in engineering mechanics from Vanderbilt University in 1975 an M.E. degree in naval architecture from the University of California Berkeley in 1981 and a Ph.D. in civil engineering (structures) from the University of Maryland in 1986. Dr. White served on active duty with the U.S. Navy from 1975 to 1979 as a junior officer in the engineering and operations departments of Pacific Fleet destroyers. Prior to coming to the Naval Academy he worked at Mare Island Naval Shipyard in the scientific code and in the R&D division of Exxon International Company's Tanker Department. Dr. White is a lieutenant commande

A methodology for the structural life assessment of a ship's structure is suggested. The methodology is based on probabilistic analysis using reliability concepts and the statistics of extremes. In this approach, the estimation of structural life expectancy is based on selected failure modes. All possible failure modes of the ship must be investigated and the most likely paths to structural failure identified. For the purpose of illustration two failure modes are considered in this study. They are plate plastic deformation and fatigue cracking. Structural life based on these two failure modes is determined for an example vessel. The methodology determines the probability of failure of the ship's structural components according to the identified failure modes as a function of time. The results can be interpreted as the cumulative probability distribution function (CDF) of structural life. Due to the unknown level of statistical correlation between failure modes, limits or bounds on the CDF of the structural life are established. The limits correspond to the extreme cases of fully correlated and independent failure modes. The CDFs of structural life are determined for two inspection strategies; namely, inspection every year and inspection every two years with a warranty inspection at the end of the first year. The meaning of the results for the case investigated in this study is that, for example, given an inspection strategy of two years and a desired life of 15 years, there is a 72% chance that the vessel will not experience enough partial damage‘ in the failure modes identified to constitute reaching the “end of structural life” as defined.

关键词： Ships

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Efficient macro-code emulation in hardwired pipelined processors 21

Efficient macro-code emulation in hardwired pipelined proces...

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Proceedings of the 21st annual workshop on Microprogramming and microarchitecture

作者： J. M. Mulder R. J. Portier A. Srivastava R. in't Velt Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology POBox 5031 2600 AG Delft The Netherlands

ISBN: (纸本)9780818619199

Traditionally microcoded computers have been the ideal machines for implementing scalable architectures. These machines easily implement application-specific functionality in microcode and they allow architecturally transparent variation of cost/performance by trading off application code, microcode, and hardware. In contrast, hardwired machines are intrinsically incapable of implementing scalability, because they only implement a single level of interpretation. Recent RISC designs have introduced architectural features which partly resolve the scalability issues. They implement architectural openendness to allow application-specific functionality to be added to the architecture (by means of coprocessors and special function units). Additionally they define functions which, depending on application, cost, and performance, can be implemented in hardware or, by means of emulation, in *** identical from an abstract point of view, scalability by means of microprogramming and by means of emulation on a hardwired machine is significantly different. This paper describes the emulation facility provided in SCARCE (SCalable architecture Experiment), a streamlined architecture specifically designed for a wide range of embedded applications, requiring high performance. While architecturally transparent, this emulation facility operates with little overhead (8 cycles), adds three control registers, and is always interruptible. By increasing the hardware investment, the overhead could be decreased to 4 cycles per trap.

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DESIGN, SIMULATION AND ANALYSIS OF RSESS NETWORK

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Science China Mathematics 1987年第1期30卷 76-88页

作者：谭小南 Academia Sinica Beijing Department of Computer Architecture Institute of Computing Technology

This paper proposes a packet switching MIMD interconnection network called RSESS (Reverse Shuffle Exchange Supershuffle) network and presents some results of simulation and analysis of it. RSESS network has low hardware complexity O(N log(logN)) and short average delay. It benefits localized communication to a great extent. With an increase in the amount of locality of communication the network delay decreases *** important properties of favouring localized communication and being adaptable to a wide range of interconnection requests make RSESS network promising for packet communilation computers in which communications are localized. Using RSESS network, we can achieve high efficiency of communication and load sharing evenness.

关键词： work net SIMULATION AND ANALYSIS OF RSESS NETWORK DESIGN

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AIR-CUSHION LANDING CRAFT NAVIGATION

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NAVAL ENGINEERS JOURNAL 1985年第4期97卷 248-260页

作者： GRAHAM, HR KIM, JC BAND, EGU FOWLER, AW Herbert R. Graham:received his degrees of B.S. in 1951 and M.S. in 1958 in aeronautical engineering from the Massachusetts Institute of Technology and the California Institute of Technology respectively. He also attended the Harvard Graduate School of Business Administration. He is presently a task manager at TRW Inc. McLean Virginia responsible for landing craft air cushion (LCAC) engineering support. Since joining TRW in 1967 he has had several technical project management and system engineering responsibilities in amphibious ships transportation and energy. He was responsible for the preliminary engineering design and cost estimates for tracked air cushion vehicles (TACVs). He has been active in several professional societies including ASNE and served as vice-chairman Los Angeles Section American Institute of Aeronautics and Astronautics. John C. Kim:received his degrees of B.S. in electrical engineering Tri-State University 1959 M.S. in electrical engineering Michigan State University 1960 and Ph.D. in electrical engineering Michigan State University. He is presently a senior staff engineer with TRW Inc. McLean Virginia where his technical experience has included communications system engineering and navigation system analysis. Since joining TRW in 1969 he has held numerous positions including section head project manager and department manager. His previous employment includes E-Systems/Melpar Division and Honeywell. Dr. Kim has been active in the IEEE Washington Chapter activities which included secretary vice-chairman and chairman of Systems Science and Cybernetics Group. Edward G.U. Band:received a B.S. degree in mechnical engineering in 1946 and a D.I.C in aeronautical engineering in 1947 at the City and Guilds College of London University. In 1951 he received an M.S. degree from Stevens Institute of Technology in fluid dynamics. After a career in the aircraft industry in England Canada and the U.S.A. he spent several years teaching in Chile and at Webb Institute of Naval Archi

Air cushion vehicles (ACVs) have operated successfully on commercial routes for about twenty years. The routes are normally quite short; the craft are equipped with radar and radio navigation aids and maintain continuous contact with their terminals. Navigation of these craft, therefore, does not present any unusual difficulty. The introduction of air cushion vehicles into military service, however, can present a very different picture, especially when external navigation aids are not available and the craft must navigate by dead reckoning. This paper considers the problems involved when navigating a high-speed air cushion vehicle by dead reckoning in conditions of poor visibility. A method is presented to assess the ACV's navigational capability under these circumstances. A figure of merit is used to determine the sensitivity of factors which affect navigation such as the range of visibility, point-to-point distance, speed, turning radius and accuracy of onboard equipment. The method provides simplistic but adequate answers and can be used effectively to compare the-capability and cost of alternative navigation concepts.

关键词： AIR CUSHION VEHICLES

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