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Introducing advanced engineering topics to freshmen students using Roomba platform

Introducing advanced engineering topics to freshmen students...

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作者： Farahmand, Farid Moslehpour, Saeid Department of Engineering Science Sonoma State University CA United States Electrical and Computer Engineering Department College of Engineering Technology and Architecture University of Hartford United States

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Theoretical treatment of sink scheduling problem in wireless sensor networks

Theoretical treatment of sink scheduling problem in wireless...

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2011 IEEE Conference on computer Communications Workshops, INFOCOM WKSHPS 2011

作者： Gu, Yu Ji, Yusheng Li, Jie Zhao, Baohua Information Systems Architecture Science Research Division National Institute of Informatics Tokyo Japan State Key Laboratory of Networking and Switching Technology Beijing 100876 China School of Computer Science Univ. of Science and Technology of China Hefei Anhui 230027 China Department of Computer Science University of Tsukuba Ibaraki 305-8573 Japan

ISBN: (纸本)9781457702488

Sink Scheduling, in the form of scheduling multiple sinks among sink sites to leverage traffic burden, is an effective mechanism for the energy-efficiency of wireless sensor networks (WSNs). Due to the inherent difficulty (NP-hard in general), existing works on this topic mainly focus on heuristic/greedy algorithms and theoretic results remain unknown. In this paper, we fill in the research blank with two algorithms. The first one is based on the Column Generation (CG). It decomposes the original problem into two sub problems and solve them iteratively to approach the optimal solution. However, due to its high computational complexity, this algorithm is only suitable for small scale networks. The other one is a polynomial-time algorithm based on relaxation techniques to obtain an upperbound, which can serve as a performance benchmark for other algorithms on this problem. Through comprehensive simulations, we evaluate the efficiency of proposed algorithms. © 2011 IEEE.

关键词： Wireless sensor networks

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An agent-based infrastructure for energy profile capture and management

An agent-based infrastructure for energy profile capture and...

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International Conference on Networking, Sensing and Control

作者： Padget, Julian Riat, Harpreet Forchhammer, Benedikt Warnier, Martijn Brazier, Frances M. T. Natarajan, Sukumar Department. of Computer Science University of Bath Claverton Down Bath United Kingdom Faculty of Technology Policy and Management Delft University of Technology Delft Netherlands Department of Architecture and Civil Engineering University of Bath Claverton Down Bath United Kingdom

ISBN: (纸本)9781424495702

Accurately monitoring changing energy usage patterns in households is a first requirement for more efficient and eco-friendly energy management. Such data is essential to the establishment of the Smart Grid, but at this stage, domestic data collection devices are still in development and monitoring-enabled domestic appliances are rare, so that any experimental software framework must be flexible and adaptable both in respect of sensor sources and developer and user requirements. These considerations have been the drivers behind the distributed agent-based platform this paper proposes. It provides: (i) a generic sensor interface that can be specialised for new devices as required, while insulating the rest of the platform from such changes, (ii) persistent unstructured (RDF) data storage, permitting both semantic annotation and semantic-based queries, independent of data sources, and (iii) a flexible, dynamic browser interface, that allows for remote configuration of the sensor platform and accessibility via a wide range of devices. Two small case studies show the utility of the approach. © 2011 IEEE.

关键词： Domestic appliances

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A linked data-driven solution to user modeling in a multi-application environment

A linked data-driven solution to user modeling in a multi-ap...

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2011 IEEE 2nd International Conference on Software Engineering and Service science, ICSESS 2011

作者： Ye, Na Zhao, Yinliang Zhao, Xia Liu, Enjie Clapworthy, Gordon School of Electronic and Information Engineering Xi'an Jiao Tong University Xi'an China School of Information and Control Engineering Xi'an University of Architecture and Technology Xi'an China Department of Computer Science and Technology University of Bedfordshire Luton United Kingdom

ISBN: (纸本)9781424496969

The User Model plays a significant role in many personalized applications. Separated user modeling results in the fragments of the user model being distributed on the Web, but user modeling in a Multi-Application Environment (MAE) is increasingly required to provide a more complete user model view and more value-added user information to all relevant applications. In this paper, a Linked Data-driven user modeling approach is proposed to create links among the user model fragments of the same user who registers in different applications and, from these, construct a virtually global user model. Through these links, user information in one application can be acquired by another. An extendible Core User Model (CUM) is presented and used to describe both the common properties and the domain-specific features of the user. The advantages and disadvantages of this approach are analyzed by comparison with other user modeling methods in MAEs. The proposed solution appears to be more feasible and to offer increased flexibility. © 2011 IEEE.

关键词： Linked data

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Silencing Hardware Backdoors

Silencing Hardware Backdoors

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IEEE Symposium on Security and Privacy

作者： Adam Waksman Simha Sethumadhavan Computer Architecture and Security Technology Laboratory Department of Computer Science Columbia University New York USA

Hardware components can contain hidden backdoors, which can be enabled with catastrophic effects or for ill-gotten profit. These backdoors can be inserted by a malicious insider on the design team or a third-party IP provider. In this paper, we propose techniques that allow us to build trustworthy hardware systems from components designed by untrusted designers or procured from untrusted third-party IP providers. We present the first solution for disabling digital, design-level hardware backdoors. The principle is that rather than try to discover the malicious logic in the design -- an extremely hard problem -- we make the backdoor design problem itself intractable to the attacker. The key idea is to scramble inputs that are supplied to the hardware units at runtime, making it infeasible for malicious components to acquire the information they need to perform malicious actions. We show that the proposed techniques cover the attack space of deterministic, digital HDL backdoors, provide probabilistic security guarantees, and can be applied to a wide variety of hardware components. Our evaluation with the SPEC 2006 benchmarks shows negligible performance loss (less than 1% on average) and that our techniques can be integrated into contemporary microprocessor designs.

关键词： Hardware Security Hardware design languages Testing Nonvolatile memory System-on-a-chip Microprocessors

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A domain partition model approach to the online fault recovery of FPGA-based reconfigurable systems

A domain partition model approach to the online fault recove...

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作者： Shang, Lihong Zhou, Mi Hu, Yu Yang, Erfu School of Computer Science and Engineering Beihang University Beijing 100191 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Electronic and Electrical Engineering University of Strathclyde Glasgow Gl 1XW United Kingdom

Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%. Copyright © 2011 The Institute of Electronics, Information and Communication Engineers.

关键词： Fault tolerance

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On comparing non-singleton type-1 and singleton type-2 fuzzy controllers for a nonlinear servo system

On comparing non-singleton type-1 and singleton type-2 fuzzy...

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IEEE Symposium on Advances in Type-2 Fuzzy Logic Systems (T2FUZZ)

作者： Ana Belén Cara Ignacio Rojas Héctor Pomares Christian Wagner Hani Hagras Department of Computer Architecture and Computer Technology University of Granada Spain Computational Intelligence Centre School of Computer Science and Electronic Engineering University of Essex UK

Uncertainty handling is a major issue for the control of real-world systems. Traditional singleton type-1 Fuzzy Logic Controllers (FLCs) with crisp inputs and precise fuzzy sets cannot fully cope with the high levels of uncertainties present in real world environments (e.g. sensor noise, environmental impacts, etc.). While non-singleton type-1 fuzzy systems can provide an additional degree of freedom through non-singleton fuzzification of the inputs, it is unclear how this capability relates to singleton type-1 and specifically interval type-2 FLCs in terms of control performance (also because the application of non-singleton type-1 FLCs is quite rare in the literature). In recent years interval type-2 FLCs employing type-2 fuzzy sets with a Footprint of Uncertainty (FOU) have become increasingly popular. This FOU provides an additional degree of freedom that can enable type-2 FLCs to handle the uncertainties associated with the inputs and the outputs of the FLCs. One of the main criticisms of singleton type-2 FLCs is that they outperform (the usually singleton-) type-1 FLCs because they - respectively their type-2 fuzzy sets, employ extra parameters, thus making improved performance an obvious result. In order to address this criticism, we have implemented a non-singleton type-1 FLC which allows a more direct comparison between the non-singleton type-1 FLC and singleton interval type-2 FLC as the number of parameters for both controllers is very similar. The paper details the implementation details of the FLCs for the application of a nonlinear servo system and provides the experimental simulation results which were performed to study the effect of increasing levels of uncertainty (in the form of input noise) and the capability of the individual FLCs to cope with them. We conclude by providing our interpretation of the results and highlighting the essential differences in the uncertainty handling between the (non-) singleton type-1 and singleton interval type-2 FLC

关键词： Uncertainty Noise Fuzzy sets Servomotors Fuzzy logic Noise measurement Pragmatics

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On fuzzy partitions for visual texture modelling

On fuzzy partitions for visual texture modelling

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IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)

作者： J. Chamorro-Martínez P. Martínez-Jiménez J. M. Soto-Hidalgo Department of Computer Science and Artificial Intelligence University of Granada Spain Department of Computer Architecture Electronics and Electrical Technology University of Córdoba Spain

Texture is one of the most used low-level feature for image analysis and, in addition, one of the most difficult to characterize due to its imprecision. It is usual for humans to describe visual textures according to some perceptual properties like coarseness-fineness, orientation or regularity. In this paper, we propose to model the fineness property, that is the most popular one, by means of a fuzzy partition on the domain of representative fineness measures. In our study, a wide variety of measures is studied, and the partitions are obtained by relating each measure (our reference set) with the human perception of fineness. Assessments about the perception of this property are collected from pools. This information is used to analyze the capability of each measure to discriminate different fineness categories, which imposes the number of fuzzy sets of the partition. Moreover, it is used to calculate the parameters of the membership function associated to each fuzzy set.

关键词： Humans Fuzzy sets Correlation Pragmatics Visualization Kernel Clustering algorithms

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CHMasters: A Scalable and Speed-Efficient Metadata Service in Distributed File System

CHMasters: A Scalable and Speed-Efficient Metadata Service i...

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Min Xu Junrui Zhou Wei Zhou Hong An Department of Computer Science and Technology University of Science and Technology of China Hefei China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China

Distributed file system (DFS) is playing important roles of supporting large distributed data-intensive applications to meet storage needs. Typically, the design of DFS, such as GFS in Google, DMS in Cisco and TFS in Alibaba, is driven by observations of specific application workloads, internal demands and technological environment. In such systems, the metadata service is a critical factor that can affect the file system performance and availability to a great degree. Five requirements have been summarized for the metadata service: location transparent file service, smart director, efficient speed, strong scalability and friendly collaborator. In this paper, we present metadata service module called CH Masters in our DFS. Consistent hashing protocol is used to relieve potential hot spots on name servers. Files' metadata and master nodes are mapped into the same hash space by consistent hash function. And then files' metadata are scattered to master nodes by clockwise "closest" principle. Chunk server acts as a client when report its chunks info. Only a small proportion of files' metadata will be rehashed when master nodes state change. A new scalable file mapping strategy is also proposed to map file sizes from few MB to several GB efficiently. After intensive experiments, it shows CH Masters is satisfying the above five requirements.

关键词： Protocols File systems Google Servers computer architecture Clocks Testing

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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations

A parallel Ray Tracing architecture suitable for application...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands

ISBN: (纸本)9780769544946

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared." © 2011 IEEE.

关键词： Ray tracing

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