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46th ICT and Electronics Convention, MIPRO 2023

作者： Solaja, Kresimir Blecic, Raul Broznic, Andro Baric, Adrijan University of Zagreb Faculty of Electrical Engineering and Computing Department of Electronics Microelectronics Computer and Intelligent Systems Zagreb Croatia Rimac Technology d.o.o./Embedded Hardware Sveta Nedelja Croatia

ISBN: (纸本)9789532331042

A 10-A automotive buck converter is designed and realized on a four layer printed circuit board. The output network is designed in the electromagnetic solver to account for the trace and package parasitic elements. The output network of the converter is simulated in the SPICE solver. The converter is characterized in the time domain by the load transient measurements and in the frequency domain by the shunt measurement method. Three configurations of the output network are compared. The results in the frequency domain and the results of the SPICE simulations are correlated. © 2023 MIPRO Croatian Society.

关键词： Time domain analysis

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Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC

arXiv

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arXiv 2024年

作者： Rogenmoser, Michael Wiese, Philip Forlin, Bruno Endres Gürkaynak, Frank K. Rech, Paolo Menicucci, Alessandra Ottavi, Marco Benini, Luca The Integrated Systems Laboratory ETH Zurich Switzerland The Computer Architecture for Embedded Systems The University of Twente Netherlands The Department of Industrial Engineering The University of Trento Italy The Department of Space Engineering The Delft University of Technology Netherlands The Computer Architecture for Embedded Systems The University of Twente Netherlands The Department of Electronic Engineering The University of Rome Tor Vergata Italy The Integrated Systems Laboratory ETH Zurich Switzerland The Department of Electrical Electronic and Information Engineering The University of Bologna Italy

We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteein... 详细信息

关键词： Fault tolerance

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VersaSens: An Extendable Multimodal Platform for Next-Generation Edge-AI Wearables

IEEE Transactions on Circuits and Systems for Artificial Int...

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IEEE Transactions on Circuits and systems for Artificial Intelligence 2024年第1期1卷 83-96页

作者： Taraneh Aminosharieh Najafi José Angel Miranda Calero Jérôme Thevenot Benjamin Duc Stefano Albini Alireza Amirshahi Hossein Taji María José Belda Beneyto Antonio Affanni David Atienza Embedded Systems Laboratory (ESL) Institute of Electrical and Micro Engineering École Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland Polytechnic Department of Engineering and Architecture Udine Italy Computer Architecture and Automation Department Universidad Complutense de Madrid Madrid Spain

The transition of healthcare towards digitalization is closely related to the advancement of health-related technologies, including wearable sensors and edge computing. In this paper, we present VersaSens, a versatile and customizable platform concept and its real implementation as a tool to boost research in wearable sensors. The platform embodies the core attributes of the VersaSens concept: versatility, flexibility, and extendability across multiple aspects of hardware, software, and processing components. It features a modular design, consisting of sensor, processor, and co-processor modules, allowing for various configurations. To evaluate the efficiency of the platform, we tested three use cases: cough monitoring, heartbeat classification and epileptic seizure detection. In all cases, the results indicate that the platform effectively executes the applications, achieving low energy consumption. In particular, our findings indicates that the integration of a domain-specific edge-AI co-processor [i.e., HEEP ocrates (Machetti et al., 2024)] equipped with several hardware accelerators further improved the overall execution time and energy consumption of the system. These results demonstrate the potential of VersaSens to effectively support a diverse range of edge-AI applications and configurations, thereby providing a robust foundation for the research and development of novel smart wearable sensor systems.

关键词： Sensors Wearable devices Artificial intelligence Wearable sensors Medical services Intelligent sensors Monitoring

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A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

TechRxiv

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TechRxiv 2023年

作者： Menbari, Ahmad Rahimi, Hemin Jahanirad, Hadi Ziener, Daniel The Department of Electrical Engineering University of Kurdistan Sanandaj Iran The Department of Computer Architecture and Embedded Systems Ilmenau University of Technology Ilmenau Germany

In the realm of 3D monolithic integrated circuits, inter-layer vias are prone to defects during fabrication, assembly, and operation that necessitates robust Built-In Self-Test solutions. This paper introduces an innovative BIST design aimed at the detection and localization of different types of faults in irregularly placed ILVs using a walking pattern methodology. In the proposed BIST methodology, the ILVs are clustered based on the fault occurrence probability distribution. Then, an effective detection approach is developed for all stuck-at faults, bridging faults, and almost all multiple faults in a single cluster. This approach allows designers to adjust different parameters such as fault coverage percentage, fault localization, and test time in alignment with specific requisites. The proposed BIST method reduces test configurations to two and test time to just 20 cycles by dividing ILVs into more clusters, overcoming a key limitation of recent approach. This methodology also demonstrates improved efficiency in terms of power consumption, area, and hardware utilization, particularly for large-scale benchmarks. For instance, when considering LU32PEENG and the scenario where ILVs are divided into 64 clusters, the power, area, and hardware overhead are 0.82% and 1.03%, and 1.14%, respectively. © 2023, CC BY.

关键词： Built-in self test

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Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC

引用

IEEE Transactions on Nuclear Science 2025年

作者： Rogenmoser, Michael Wiese, Philip Forlin, Bruno Endres Gurkaynak, Frank K. Rech, Paolo Menicucci, Alessandra Ottavi, Marco Benini, Luca Integrated Systems Laboratory ETH Zurich Switzerland Computer Architecture for Embedded Systems University of Twente Netherlands Department of Industrial Engineering University of Trento Italy Delft University of Technology Department of Space Engineering Netherlands University of Rome Department of Electronic Engineering Tor Vergata Italy Information Engineering at the University of Bologna Department of Electrical Electronic Italy

RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires characterization under controlled radiation doses to accurately quantify the fault tolerance of the fabricated designs. This work analyzes the Trikarenos design, a SoC implemented in TSMC 28nm, for single event upset (SEU) vulnerability under atmospheric neutron and 200MeV proton radiation, comparing these results to simulation-based fault injection. All faults in error correction codes (ECC) protected memory are corrected by a scrubber, showing an estimated cross-section per bit of up to 1.09 × 10−14 cm2 bit−1. Furthermore, the triple-core lockstep (TCLS) mechanism implemented in Trikarenos is validated and is shown to correct errors affecting a cross-section up to 3.23 × 10−11 cm2, with the remaining uncorrectable vulnerability below 5.36 × 10−12 cm2. When augmenting the experimental analysis of fabricated chips with gate-level fault injection in simulation, 99.10% of injections into the SoC produced correct results, while 100% of injections in the TCLS-protected cores were handled *** 12.28%of all injected faults leading to a TCLS recovery, this indicates an approximate effective flip-flop cross-section of up to 1.28 × 10−14 cm2/FF. © 1963-2012 IEEE.

关键词： Radiation damage

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Design and Characterization of the Output Network of a High-Current Buck Converter

Design and Characterization of the Output Network of a High-...

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Proceedings of the International Convention MIPRO

作者： Krešimir Šolaja Raul Blečić Andro Broznić Adrijan Barić Department of Electronics Microelectronics Computer and Intelligent Systems Faculty of Electrical Engineering and Computing University of Zagreb Zagreb Croatia Rimac Technology d.o.o./Embedded Hardware Sveta Nedelja Croatia

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An FPGA-based 7-ENOB 600 msample/s adc without any external components 21

An FPGA-based 7-ENOB 600 msample/s adc without any external ...

引用

2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2021

作者： Leuenberger, Lukas Amiet, Dorian Wei, Tao Zbinden, Paul OST-Eastern Switzerland University of Applied Sciences Imes Institute for Microelectronics and Embedded Systems Rapperswil Switzerland University of Rhode Island Department of Electrical Computer and Biomedical Engineering Kingston United States

ISBN: (纸本)9781450382182

Analog to digital converters (ADCs) are indispensable nowadays. Analog signals are digitized earlier and earlier in the processing chain to reduce the need for complex analog signal processing. For this reason, ADCs are often integrated directly into field-programmable gate arrays (FPGA) or microprocessors. However, such ADCs are designed for a specific set of requirements with limited flexibility. In this paper, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured. Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC. Considering the very high number of digital I/O ports available in today's FPGA systems, this enables the construction of a massive and powerful ADC array directly on a standard FPGA. The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. The differential nonlinearity (DNL) ranges from-0.9 to 0.9 bit, and the integral nonlinearity (INL) is in the range between-1.1 and 0.9 bit. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3. © 2021 ACM.

关键词： Signal processing

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Novel Approaches for ML-Assisted Particle Track Reconstruction and Hit Clustering

arXiv

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arXiv 2024年

作者： Odyurt, Uraz Dobreva, Nadezhda Wolffs, Zef Zhao, Yue Sánchez, Antonio Ferrer de Austri Bazan, Roberto Ruiz Martín-Guerrero, José D. Varbanescu, Ana-Lucia Caron, Sascha High-Energy Physics department Radboud University Netherlands Netherlands SURF Netherlands Instituto de Física Corpuscular University of Valencia Spain IDAL Department of Electronic Engineering ETSE-UV University of Valencia Spain Spain Computer Architecture for Embedded Systems University of Twente Netherlands

Track reconstruction is a vital aspect of High-Energy Physics (HEP) and plays a critical role in major experiments. In this study, we delve into unexplored avenues for particle track reconstruction and hit clustering. Firstly, we enhance the algorithmic design effort by utilising a simplified simulator (REDVID) to generate training data that is specifically composed for simplicity. We demonstrate the effectiveness of this data in guiding the development of optimal network architectures. Additionally, we investigate the application of image segmentation networks for this task, exploring their potential for accurate track reconstruction. Moreover, we approach the task from a different perspective by treating it as a hit sequence to track sequence translation problem. Specifically, we explore the utilisation of Transformer architectures for tracking purposes. Our preliminary findings are covered in detail. By considering this novel approach, we aim to uncover new insights and potential advancements in track reconstruction. This research sheds light on previously unexplored methods and provides valuable insights for the field of particle track reconstruction and hit clustering in HEP. © 2024, CC BY.

关键词： High energy physics

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Automated Sensor Firmware Development - Generation, Optimization, and Analysis 22

Automated Sensor Firmware Development - Generation, Optimiza...

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22. Workshop on Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2019 - 22nd Workshop on Methods and Description Languages for Modeling and Verification of Circuits and systems, MBMV 2019

作者： Rudolf, Jens Strobel, Manuel Benz, Joscha Haubelt, Christian Radetzki, Martin Bringmann, Oliver Institute of Applied Microelectronics and Computer Engineering University of Rostock Rostock18051 Germany Chair of Embedded Systems University of Stuttgart Stuttgart70569 Germany Embedded Systems Department University of Tübingen Tübingen72076 Germany

ISBN: (纸本)9783800749461

embedded systems design has lately become particularly challenging due to fast increasing system complexities, real-time demands and reliability requirements. At the same time, designs are constrained by stringent power budgets, limited memory capacity and short time-to-markets. Recently, various methods to automatically generate, analyze, and optimize different stages of the design flow have been investigated. The evaluation of these methods, however, often focuses on a single associated field of research and thus may not consider the domain-crossing effects that stem from the interaction of different design methods. This paper presents a complete and fully automated workflow that covers model-based generation, analysis, and optimization aspects for embedded firmware and demonstrates it on a virtual system prototype of a typical inertial sensor node. We illustrate the integration of different design and evaluation methods on a realistic example and show potential opportunities for the application of gathered information in order to improve the design. © MBMV 2019 - 22. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen". All rights reserved.

关键词： Firmware

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Automated Sensor Firmware Development - Generation, Optimization, and Analysis

Automated Sensor Firmware Development - Generation, Optimiza...

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MBMV 2019;22nd Workshop - Methods and Description Languages for Modelling and Verification of Circuits and systems

作者： Jens Rudolf Manuel Strobel Joscha Benz Christian Haubelt Martin Radetzki Oliver Bringmann Institute of Applied Microelectronics and Computer Engineering University of Rostock Chair of Embedded Systems University of Stuttgart Embedded Systems Department University of Tubingen

ISBN: (纸本)9783800749454

embedded systems design has lately become particularly challenging due to fast increasing system complexities, realtime demands and reliability requirements. At the same time, designs are constrained by stringent power budgets, limited memory capacity and short time-to-markets. Recently, various methods to automatically generate, analyze, and optimize different stages of the design flow have been investigated. The evaluation of these methods, however, often focuses on a single associated field of research and thus may not consider the domain-crossing effects that stem from the interaction of different design methods. This paper presents a complete and fully automated workflow that covers model-based generation, analysis, and optimization aspects for embedded firmware and demonstrates it on a virtual system prototype of a typical inertial sensor node. We illustrate the integration of different design and evaluation methods on a realistic example and show potential opportunities for the application of gathered information in order to improve the design.

关键词： Design flow power budget Firmware evaluation method memory capacity embedded systems Automation Analysis Sensors Virtual systems

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