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Self-Awareness for Autonomous systems

PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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A dataflow inspired programming paradigm for coarse-grained reconfigurable arrays

A dataflow inspired programming paradigm for coarse-grained ...

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10th International Symposium on Reconfigurable Computing: architectures, Tools, and Applications, ARC 2014

作者： Niedermeier, A. Kuper, Jan Smit, Gerard J. M. Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente Netherlands

ISBN: (纸本)9783319059594

In this paper, we present a new approach towards programming coarse-grained reconfigurable arrays (CGRAs) in an intuitive, dataflow inspired way. Based on the observation that available CGRAs are usually programmed using C, which lacks proper support for instruction-level parallelism, we instead started from a dataflow perspective combined with a language that inherently supports parallel structures. Our programming paradigm decouples the local functionality of a core from the global flow of data, i.e. the kernels from the routing. We will describe the ideas of our programming paradigm and also the language and compiler itself. Our complete system, including the CGRA, the programming language and the compiler, was developed using Haskell, which leads to a complete, sound system. We finish the paper with the implementation of a number of algorithms using our system. © 2014 Springer International Publishing Switzerland.

关键词： Program compilers

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Automatic complex instruction identification for efficient application mapping onto ASIPs

Automatic complex instruction identification for efficient a...

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IEEE Latin American Symposium on Circuits and systems (LASCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M. G. França Lech Jozwiak Henk Corporaal Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology The Netherlands Department of Electronics Engineering and Telecommunications Universidade do Estado do Rio de Janeiro Brazil LAM - Computer Architecture and Microelectronics Laboratory Universidade Federal do Rio de Janeiro Brazil

Instruction Set Customization is a well-known technique to enhance the performance and efficiency of Application-Specific Processors (ASIPs). An extensive application profiling can indicate which parts of a given application, or class of applications, are most frequently executed, enabling the implementation of such frequently executed parts in hardware as custom instructions. However, a naive ad hoc instruction set customization process may identify and select poor instruction extension candidates, which may not result in a significantly improved performance with low circuit-area and energy footprints. In this paper we propose and discuss an efficient instruction set customization method and automatic tool, which exploit the maximal common subgraphs (common operation patterns) of the most frequently executed basic blocks of a given application. The speed results from our tool for a VLIW ASIP are provided for a set of benchmark applications. The average execution time reduction ranges from 30% to 40%, with only a few custom instructions.

关键词： VLIW Hardware Ray tracing Program processors Registers Libraries Convolution

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A framework for automatic custom instruction identification on multi-issue ASIPs

A framework for automatic custom instruction identification ...

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IEEE International Conference on Industrial Informatics (INDIN)

作者： Alexandre S. Nery Nadia Nedjah Felipe M. G. França Lech Jozwiak Henk Corporaal LAM - Computer Architecture and Microelectronics Laboratory COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology The Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

Custom Instruction Identification is an important part in the design of efficient Application-Specific Processors (ASIPs). It consists of profiling of a given application to find patterns of basic operations that are frequently executed. Operations of such patterns can be implemented together as a single custom instruction to speedup the execution of the application. Because of the problem's high complexity, several methods have been proposed for specific single-issue (RISC) processors and architectures, limiting the shape and size of custom instructions that can actually be identified and, possibly, implemented. In this paper, we propose and discuss an efficient custom instruction set identification method and corresponding automatic tool for multi-issue VLIW ASIPs, which search for the common operation patterns of the most frequently executed basic blocks of a given application, with different sizes and shapes. The speedup results for the custom instructions identified by our tool are provided for a set of benchmark applications. The speedup is up to 68%, with only a few custom instructions used.

关键词： VLIW Program processors Libraries Registers Ray tracing Hardware Shape

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A predictor-based power-saving policy for DRAM memories

A predictor-based power-saving policy for DRAM memories

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15th Euromicro Conference on Digital System Design, DSD 2012

作者： Thomas, Gervin Chandrasekar, Karthik Åkesson, Benny Juurlink, Ben Goossens, Kees Technische Universität Berlin Department of Computer Engineering and Microelectronics Embedded Systems Architecture Berlin Germany Technische Universiteit Delft Department of Computer Engineering Delft Netherlands Technische Universiteit Eindhoven Department of Electrical Engineering Electronic Systems Eindhoven Netherlands

ISBN: (纸本)9780769547985

Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings. In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%. © 2012 IEEE.

关键词： Dynamic random access storage

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Parallel VLSI detailed routing using general-purpose computing on graphics processing unit

Parallel VLSI detailed routing using general-purpose computi...

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2012 9th International Conference on Electrical engineering/Electronics, computer, Telecommunications and Information Technology, ECTI-CON 2012

作者： Tangjittaweechai, Lalinthip Ekpanyapong, Mongkol Kanchanasut, Kanchana Tavares, Adriano Lim, Sung Kyu Chongstitvatana, Prabhas Microelectronics and Embedded Systems Asian Institute of Technology Pathumthani Thailand Computer Science Department Asian Institute of Technology Pathumthani Thailand Department of Industrial Electronics University of Minho Guimarães Portugal School of Electrical and Computer Engineering Georgia Institute of Technology GA United States Computer Engineering Department Chulalongkorn University Bangkok Thailand

ISBN: (纸本)9781467320245

Parallelization of VLSI routing algorithms is one of the challenging problems in VLSI physical design. This is due to a large number of nets as well as the shared routing resources that result in data dependency among concurrent tasks. In this paper, VLSI Maze routing using GPGPU has been proposed to enable runtime performance improvement. We report up to 3x performance gain with an average of 25% runtime performance improvement from VLSI Maze routing using CPU. The routing qualities including wirelength and overflow are better among all benchmarks comparing with CPU baseline. The solutions also scale well when the size of the problem increases. © 2012 IEEE.

关键词： Graphics processing unit

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A Predictor-Based Power-Saving Policy for DRAM Memories

A Predictor-Based Power-Saving Policy for DRAM Memories

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Euromicro Symposium on Digital System Design

作者： Gervin Thomas Karthik Chandrasekar Benny Åkesson Ben Juurlink Kees Goossens Department of Computer Engineering and Microelectronics Embedded Systems Architecture Technische Universität Berlin Berlin Germany Department of Computer Engineering Technische Universiteit Delft Delft Netherlands Department of Electrical Engineering Electronic Systems Technische Universiteit Eindhoven Eindhoven Netherlands

关键词： Random access memory History Clocks Energy consumption Prediction algorithms Memory management Servers

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Parallel VLSI detailed routing using general-purpose computing on graphics processing unit

Parallel VLSI detailed routing using general-purpose computi...

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International Conference on Electrical engineering/Electronics, computer, Telecommunications and Information Technology, ECTI-CON

作者： Lalinthip Tangjittaweechai Mongkol Ekpanyapong Kanchana Kanchanasut Adriano Tavares Sung Kyu Lim Prabhas Chongstitvatana Microelectronics and Embedded Systems Asian Institute of Technology Pathumthani Thailand Computer Science department Asian Institute of Technology Pathumthani Thailand School of Electrical and Computer Engineering Georgia Institute of Technology Georgia USA Department of Industrial Electronics University of Minho Guimaraes Portugal Computer Engineering department Chulalongkorn University Bangkok Thailand

Parallelization of VLSI routing algorithms is one of the challenging problems in VLSI physical design. This is due to a large number of nets as well as the shared routing resources that result in data dependency among concurrent tasks. In this paper, VLSI Maze routing using GPGPU has been proposed to enable runtime performance improvement. We report up to 3× performance gain with an average of 25% runtime performance improvement from VLSI Maze routing using CPU. The routing qualities including wirelength and overflow are better among all benchmarks comparing with CPU baseline. The solutions also scale well when the size of the problem increases.

关键词： Routing Instruction sets Graphics processing unit Very large scale integration Central Processing Unit Benchmark testing Runtime

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Adaptive resource allocation for streaming applications

Adaptive resource allocation for streaming applications

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2011 11th International Conference on embedded computer systems: architectures, Modeling and Simulation, IC-SAMOS 2011

作者： Ter Braak, Timon D. Toersche, Hermen A. Kokkeler, André B.J. Smit, Gerard J.M. Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente P.O. Box 217 7500 AE Enschede Netherlands

ISBN: (纸本)9781457708008

Streaming applications often have latency and throughput requirements due to timing critical signal processing, or the time critical interaction with their environment. Mapping such applications to a multi-core architecture is commonly done at design-time to be able to analyze the complex design-space. However, such design-flows cannot deal with a dynamic platform or a dynamic set of applications. Hardware faults and resources claimed by other applications may render the assumed available resources inaccessible. To avoid the assumptions posed on the state of the platform by a fixed resource allocation, applications should be designed with location transparency in mind. Applications must be analyzed at design-time to determine the required resource budget, independent of which specific resources will be allocated. Sufficient performance can be guaranteed when such applications are mapped onto an architecture in which each resource is arbitrated using a budget scheduler. Within the Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project, a many-core platform is developed that adheres to these requirements. Using the configuration features of the platform, the system is able to control at run-time what resources are being used by the applications. This paper shows that run-time resource allocation can effectively adapt to the available set of resources, providing partial distribution transparency to the user. As an example, a GNSS receiver is mapped to the platform containing faulty hardware components. A few resources remain critical, but in most cases the faulty components can be circumvented, such that adequate resources can be allocated to the application at run-time. © 2011 IEEE.

关键词： Budget control

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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations

A parallel Ray Tracing architecture suitable for application...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands

ISBN: (纸本)9780769544946

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared." © 2011 IEEE.

关键词： Ray tracing

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