检索结果-内蒙古大学图书馆

2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

来源：评论

学校读者我要写书评

暂无评论

Adaptive resource allocation for streaming applications

Adaptive resource allocation for streaming applications

引用

International Conference on embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Timon D. ter Braak Hermen A. Toersche André B. J. Kokkeler Gerard J. M. Smit Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente Enschede Netherlands

Streaming applications often have latency and throughput requirements due to timing critical signal processing, or the time critical interaction with their environment. Mapping such applications to a multi-core architecture is commonly done at design-time to be able to analyze the complex design-space. However, such design-flows cannot deal with a dynamic platform or a dynamic set of applications. Hardware faults and resources claimed by other applications may render the assumed available resources inaccessible. To avoid the assumptions posed on the state of the platform by a fixed resource allocation, applications should be designed with location transparency in mind. Applications must be analyzed at design-time to determine the required resource budget, independent of which specific resources will be allocated. Sufficient performance can be guaranteed when such applications are mapped onto an architecture in which each resource is arbitrated using a budget scheduler. Within the Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project, a many-core platform is developed that adheres to these requirements. Using the configuration features of the platform, the system is able to control at run-time what resources are being used by the applications. This paper shows that run-time resource allocation can effectively adapt to the available set of resources, providing partial distribution transparency to the user. As an example, a GNSS receiver is mapped to the platform containing faulty hardware components. A few resources remain critical, but in most cases the faulty components can be circumvented, such that adequate resources can be allocated to the application at run-time.

关键词： Hardware Routing Resource management Global Navigation Satellite systems Receivers Tiles Radio frequency

来源：评论

学校读者我要写书评

暂无评论

A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

来源：评论

学校读者我要写书评

暂无评论

Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

引用

Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management computer architecture Optimization Program processors Adders Delay

来源：评论

学校读者我要写书评

暂无评论

A Parallel Ray Tracing architecture Suitable for Application-Specific Hardware and GPGPU Implementations

A Parallel Ray Tracing Architecture Suitable for Application...

引用

Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Nadia Nedjah Felipa M.G. Franca Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

关键词： Ray tracing Graphics processing unit Instruction sets computer architecture Registers Image color analysis Hardware

来源：评论

学校读者我要写书评

暂无评论

A massively parallel hardware architecture for ray-tracing

引用

International Journal of High Performance systems architecture 2009年第1期2卷 26-34页

作者： Nery, A.S. Nedjah, N. França, F.M.G. Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE P.O. Box 68511 21941-972 Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20.550-900 Rio de Janeiro RJ Brazil Universidade Federal do Rio de Janeiro Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil Brazil

Real time performance of non-interactive rendering of three-dimensional scenes is usually unachievable. Ray tracing is one of the methods used for rendering such scenes. The performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. In contrast, many parallel implementations of ray tracing have been enabling real time performance, as the underlying algorithm can be massively parallelised. Thus, it is expected that a custom parallel design in hardware is likely to achieve the acceptable performance standards. In this paper, we propose a hardware architecture, which we call GridRT, capable of dealing with the main desirable features of ray tracing, such as shadows and reflections effects, imposing low requirements in terms of silicon area while achieving acceptable performance in terms of rendering time. This architecture achieves is efficient yet compact as it explores the massive parallelism offered by the intrinsic structure of the algorithm. The design exploits the usage the spatial data structure of regular grids. Copyright © 2009 Inderscience Enterprises Ltd.

关键词： Ray tracing

来源：评论

学校读者我要写书评

暂无评论

Dynamic thermal management in 3D multicore architectures 09

Dynamic thermal management in 3D multicore architectures

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Ayse K. Coskun Jose L. Ayala David Atienza Tajana Simunic Rosing Yusuf Leblebici Computer Science and Engineering Department (CSE) University of California San Diego USA Computer Architecture and Automation Department (DACYA) Complutense University of Madrid Spain Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne Switzerland Microelectronics Systems Laboratory (LSM) EPF Lausanne Switzerland

ISBN: (纸本)9783981080155

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units on top of each other. In this work, we first investigate how the existing thermal management, power management and job scheduling policies affect the thermal behavior in 3D chips. We then propose a dynamic thermally-aware job scheduling technique for 3D systems to reduce the thermal problems at very low performance cost. Our approach can also be integrated with power management policies to reduce energy consumption while avoiding the thermal hot spots and large temperature variations.

关键词： Thermal management Multicore processing Energy management Power system management Energy consumption Processor scheduling Transistors computer architecture Delay Wires

来源：评论

学校读者我要写书评

暂无评论

Modeling and dynamic management of 3D multicore systems with liquid cooling

Modeling and dynamic management of 3D multicore systems with...

引用

IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Ayse K. Coskun José L. Ayala David Atienza Tajana Simunic Rosing Computer Science and Engineering Department (CSE) University of California San Diego USA Computer Architecture and Automation Department (DACYA) Complutense University of Madrid Spain Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne (EPFL) Switzerland

Three-dimensional (3D) circuits reduce communication delay in multicore SoCs, and enable efficient integration of cores, memories, sensors, and RF devices. However, vertical integration of layers exacerbates the reliability and thermal problems, and cooling efficiency becomes a limiting factor. Liquid cooling is a solution to overcome the accelerated thermal problems imposed by multi-layer architectures. In this paper, we first provide a 3D thermal simulation model including liquid cooling, supporting both fixed and variable fluid injection rates. Our model has been integrated in HotSpot to study the impact on multicore SoCs. We design and evaluate several dynamic management policies that complement liquid cooling. Our results for 3D multicore SoCs, which are based on 3D versions of UltraSPARC T1, show that thermal management approaches that combine liquid cooling with proactive task allocation are extremely effective in preventing temperature problems. Our proactive management technique provides an additional 75% average reduction in hot spots in comparison to applying only liquid cooling. Furthermore, for systems capable of varying the coolant flow rate at runtime, our feedback controller increases the improvement to 95% on average.

关键词： Three dimensional displays Liquid cooling Thermal management Microchannel Through-silicon vias Thermal resistance

来源：评论

学校读者我要写书评

暂无评论

Appointments for 2005-2006 term

引用

IEEE Transactions on Very Large Scale Integration (VLSI) systems 2005年第7期13卷 773-782页

作者： Ranganathan, Nagarajan Agrawal, Vishwani D. Chakradhar, Srimat T. Chakrabarty, Krishnendu Courtois, Bernard DeMara, Ronald Hu, Xiaobo Sharon Ismail, Yehea I. Jha, Niraj K. John, Lizy Kurian Ker, Ming-Dou Koren, Israel Liu, Bin-Da Marculescu, Diana Marculescu, Radu Narayanan, Vijaykrishnan Nassif, Sani R. Nowick, Steven M. Sapatnekar, Sachin S. Sherlekar, Sunil Sylvester, Dennis Vemuri, Ranga Pham, Michael Department of Computer Science and Engineering University of South Florida Tampa FL 33620 United States Department of Computer Science and Engineering Nanomaterials and Nanomanufacturing Research Center University of South Florida Tampa United States IEEE United States Systems United States Department of Electrical and Computer Engineering Rutgers University New Brunswick NJ United States IETE India ACM NEC Laboratories America Inc. Princeton NJ United States Duke University Durham NC United States ACM SIGDA Sigma Xi United States Laboratory of Techniques of Informatics and Microelectronics for Computer Architectecture ASME IMAPS IEEE Computer Society University of Central Florida Orlando United States Computer Engineering Program SEECS Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Northwestern University Evanston IL United States Department of Electrical Engineering Princeton University Princeton NJ United States Association for Computing Machinery Austin United States UT Austin Engineering Foundation United States Department of Electronics Engineering National Chiao-Tung University Taiwan Department of Electrical and Computer Engineering University of Massachusetts Amherst United States Department of Electrical Engineering Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA United States Electrical and Computer Engineering Faculty Carnegie Mellon University Pittsburgh PA United States Computer Science and Engineering Department Pennsylvania State University University Park United States IBM Austin Research Laboratory Austin TX United States Columbia University New York NY United States Department of Electrical and Computer Engineering University of Minnesota Minneapolis United States Tata Consultancy Services Centre of Excellence for Embedded Systems India Department of Electrical Engineering IIT Bombay India Department of Electrical Engineering Uni

No abstract available

关键词：

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：