The development of communication systems in the past years has increased the necessity to synthesize very accurate clocks, having large frequencies and very low jitter. In the same large numbers expresses the divide r...
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The development of communication systems in the past years has increased the necessity to synthesize very accurate clocks, having large frequencies and very low jitter. In the same large numbers expresses the divide ratios between the frequencies of the clocks that we have to synchronize. This paper presents a new type of circuit named Direct Digitally Delay Generator (DDDG), able to synthesize frequencies up to 1 GHz with a jitter below 200 ps.
In this paper we present the search and determination of a subset of orthogonal convolutional codes called convolutional self doubly orthogonal codes (CSO/sup 2/C). These codes may be advantageously utilised for the n...
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In this paper we present the search and determination of a subset of orthogonal convolutional codes called convolutional self doubly orthogonal codes (CSO/sup 2/C). These codes may be advantageously utilised for the novel coding/iterative decoding technique introduced as an important amelioration of turbo codes. For this technique the code constraint length corresponds to the latency of each decoding iteration. Hence, an important parameter in the code searching is the minimisation of the code constraint length for a given error correcting capability.
Presents a fully integrated CMOS fast phase locked loop (PLL), based on a new wide swing differential voltage controlled oscillator (WSDVCO). The proposed PLL incorporates new simple architecture of well known PLL bui...
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Presents a fully integrated CMOS fast phase locked loop (PLL), based on a new wide swing differential voltage controlled oscillator (WSDVCO). The proposed PLL incorporates new simple architecture of well known PLL building blocks (a dynamic phase-frequency detector, a charge pump, an on-chip low-pass filter, a WSDVCO and a frequency divider). The present version of the WSDVCO allows one to obtain wide tuning range of 40 to 730 MHz simulated with Spectre simulator using 0.25 /spl mu/m CMOS technology. The simplicity of the proposed PLL building blocks permits one to design high performance PLL.
This paper presents a digitally controlled RF predistorter suitable for power amplifiers operating in different traffic and load conditions. The developed digital controlled RF predistorter has enough control paramete...
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Conditional compilation is one of the most powerful parts of a C/C++ environment available for building software for different platforms with different feature sets. Although conditional compilation is powerful, it ca...
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Conditional compilation is one of the most powerful parts of a C/C++ environment available for building software for different platforms with different feature sets. Although conditional compilation is powerful, it can be difficult to understand and is error-prone. In large software systems, file inclusion, conditional compilation and macro substitution are closely related and are often largely interleaved. Without adequate tools, understanding complex header files is a tedious task. This practice may even be complicated as the hierarchies of header files grow with projects. This paper presents our experiences of studying conditional compilation based on the symbolic execution of preprocessing directives. Our two concrete goals are: for any given preprocessor directive or C/C++ source code line, finding the simplest sufficient condition to reach/compile it, and finding the full condition to reach/compile that code line. Two different strategies were used to achieve these two goals. A series of experiments conducted on the Linux kernel are presented.
One original purpose of FACTS controllers is to increase the transmission capacity of existing lines thus deferring the necessity of building new lines. FACTS, such as the unified power flow controller (UPFC), have al...
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One original purpose of FACTS controllers is to increase the transmission capacity of existing lines thus deferring the necessity of building new lines. FACTS, such as the unified power flow controller (UPFC), have also been regarded as controllers for routing power in the market-driven, deregulated power systems. Hitherto, the UPFC has been conceived to control the complex powers through a radial line. This paper presents the concept of a multi-terminal UPFC (M-UPFC), which serves to control the complex powers of several transmission lines converging towards (or radiating from) a transmission node. In order to show that a M-UPFC can be built, that it has stable operation and that it has all the control degrees of freedom of UPFCs, a laboratory model based on 3 units of 3-phase, voltage-source converters has been assembled and tested.
Describes a low-noise, low-power and low-voltage amplifier dedicated to very low amplitude signal acquisition from implantable electronic devices. Low noise and low DC offset are realized by means of chopper stabiliza...
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Describes a low-noise, low-power and low-voltage amplifier dedicated to very low amplitude signal acquisition from implantable electronic devices. Low noise and low DC offset are realized by means of chopper stabilization (CHS) technique. In addition, due to adding a rail to rail input stage, low power supply (1.8V) and wide common mode input range (0-1.8V) are achieved. It features a gain of 51dB and a bandwidth of 4.5 kHz. The equivalent input noise is about 56nv//spl radic/(Hz).
We propose in this paper a new architecture of a CMOS integrated pulse width modulator (PWM) used to control the duty-cycle of square waveforms. The architecture of the proposed PWM is based mainly on an improved volt...
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ISBN:
(纸本)0780365429
We propose in this paper a new architecture of a CMOS integrated pulse width modulator (PWM) used to control the duty-cycle of square waveforms. The architecture of the proposed PWM is based mainly on an improved voltage controlled-delay line (VCDL) which requires a very small integrated area. The first version of this PWM allows duty-cycle control range of 0% to 50%, and the second version with duty-cycle control this range from 0% to 100%. The two versions of the proposed PWM are dedicated for the control of the power level of switching power amplifiers and are suitable for integrated DC-DC voltage conversion applications. Hspice simulation results show that the proposed PWM is able to achieve a large duty-cycle control range with high resolution.
A method for analyzing the error performance of the iterative threshold decoder using strict sense multiorthogonal convolutional codes where the multiplicity order is larger or equal to the number of iterations is pre...
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A method for analyzing the error performance of the iterative threshold decoder using strict sense multiorthogonal convolutional codes where the multiplicity order is larger or equal to the number of iterations is presented. This allows a tractable analysis, since all random variables are considered independent at each decoding step. The analysis provides a good prediction of the error probability convergence value of the iterative decoding process using strict sense doubly orthogonal convolutional codes.
This paper presents a powerful adaptive based band/RF predistorter, which uses advantageously the concept of digital receiver technology into power amplifier (PA) linearization area. The linearizer performs an instant...
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This paper presents a powerful adaptive based band/RF predistorter, which uses advantageously the concept of digital receiver technology into power amplifier (PA) linearization area. The linearizer performs an instantaneous characterization of the PA using two digital receivers to supply its AM-AM and AM-PM transfer functions. W-CDMA signals applying different stress levels on PA are used to evaluate the performance of the predistorter. The entire system is validated using DSP/RF co-simulation for a typical class AB power amplifier. Results from different cases of standards signals reveal a significant reduction in effective output power back off (OBO).
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