We propose a new circuit technique dedicated to improve the performance of the frequency and phase locked loops (FLLs & PLLs). The presented technique is based on the use of a delay-locked loop (DLL) to improve th...
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We propose a new circuit technique dedicated to improve the performance of the frequency and phase locked loops (FLLs & PLLs). The presented technique is based on the use of a delay-locked loop (DLL) to improve the speed of the basic architecture of an FLL or a PLL. The DLL is designed to lock on the input reference frequency and its control voltage is used to bias the voltage-controlled oscillator (VCO) of the FLL or the PLL. Since the DLL is unconditionally stable and its locking time is very short, the speed of the modified FLL or a PLL is automatically improved. Moreover, besides the speed improvement, all the other performances such as the phase noise (jitter), the bandwidth and the frequency locking range of the modified FLL or a PLL are not altered and are determined only by their basic architectures.
A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by ...
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A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.
The concept of system-on-a-chip is becoming increasingly popular for the integration of complex systems. New types of processor cores are now available that enable the designer to customize their processors for the ta...
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The concept of system-on-a-chip is becoming increasingly popular for the integration of complex systems. New types of processor cores are now available that enable the designer to customize their processors for the target applications. These soft cores are not tightly coupled with the target application, and this leads to processing cores sub-optimal for their specific applications. This paper proposes a method to derive application-specific embedded processors from soft processor cores. The derivation process involves an analysis of the resources of the processing core used by the target application. Then a series of optimizations based on the analysis results are performed on an optimizable model of the processor core. We present the tool used to perform the analysis of the resources used by an application, and results from a real-world case. Then, various optimization methods are described.
The concept of mobile communication networks runs into all sorts of problems. This paper presents the problems of assignment of the cells to switches in personal communication networks and proposes the application of ...
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The concept of mobile communication networks runs into all sorts of problems. This paper presents the problems of assignment of the cells to switches in personal communication networks and proposes the application of the Tabu search heuristic as a procedure for the quasi-optimal assignment in relation to hand-off. In general, the results obtained predict good behaviour of the Tabu search method.
This paper develops a traffic simulator for urban mobile network of Manhattan type. This simulator permitted the performance of a network to be measured by varying its parameters. Many interesting conclusions resulted...
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This paper develops a traffic simulator for urban mobile network of Manhattan type. This simulator permitted the performance of a network to be measured by varying its parameters. Many interesting conclusions resulted from the simulations. For instance, when some channels of each cell are reserved for handoffs, a consequent decrease in the loss probability for current calls has been observed. However, in order to not excessively penalize new calls, the number of reserved channels should not exceed half of the total number of channels. On the other hand, the remarkable aspect evidenced by these simulations is the significant improvement of the network performance, thereby a greater quality of service supplied to subscribers, when dynamic frequency assignment is used. Therefore, the improvements of network performance are not proportional to the number of cells consulted during the frequency assignment process.
AC/DC converters generate harmonic currents in power systems. A detailed analysis of harmonic currents produced by AC/DC power converters under nonideal operating conditions can be quite time consuming. In this paper,...
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AC/DC converters generate harmonic currents in power systems. A detailed analysis of harmonic currents produced by AC/DC power converters under nonideal operating conditions can be quite time consuming. In this paper, a simple analytical method is proposed for calculating harmonic currents produced by a twelve-pulse AC/DC thyristor converter under unbalanced supply voltage. Simplified models of magnitudes and phase angles of harmonic currents are derived as function of complex voltage unbalanced factor assuming equidistant phase angle control. Simulation results are presented to confirm the validity of the analytical method.
A SEF (software exchange format), such as GXL (Holt et al., 2000), TA (Holt, 1997) or RSF (Wong, 1996), is used to exchange data between tools that analyze software. Researchers at Bell Canada have specified the Datri...
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A SEF (software exchange format), such as GXL (Holt et al., 2000), TA (Holt, 1997) or RSF (Wong, 1996), is used to exchange data between tools that analyze software. Researchers at Bell Canada have specified the Datrix SEF in TA (and soon to be, GXL) for C, C++ and Java. It is designed so that a parser for the language, C, C++ or Java, can read a source program and emit the program's abstract syntax tree (AST) in the Datrix format. This note explains how an entity/relation (E/R) schema (Chen, 1976) was extracted for Datrix, and gives this schema as an E/R diagram.
The fuzzy ARTMAP neural network is used to classify data that is incomplete in one or more ways. These include a limited number of training cases, missing components, missing class labels, and missing classes. Modific...
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The fuzzy ARTMAP neural network is used to classify data that is incomplete in one or more ways. These include a limited number of training cases, missing components, missing class labels, and missing classes. Modifications for dealing with such incomplete data are introduced, and performance is assessed on an emitter identification task using a database of radar pulses.
This paper focuses on the issues involved when multiple mobile agents interact in multiagent systems. The application is an intelligent agent market place, where buyer and seller agents cooperate and compete to proces...
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Unified and complete circuit model is formulated for accurate representation of a large variety of microstrip (MS)-fed slot antenna with arbitrary width and shape. It is realized by applying a so-called "short-op...
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