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European Conference on Design Automation

作者： Y. Blaquiere M. Dagenais Y. Savaria Dept. of Math. & Comput. Sci. Univ. du Quebec Montreal Que. Canada Electrical and Computer Engineering Department École Polytechnique de Montréal Montreal QUE Canada

A new and efficient procedure to evaluate the timing performance of VLSI circuits with circuit level accuracy is proposed. The efficiency is obtained by rapidly identifying the critical portions of the circuit at high hierarchical levels with rough delay models. These portions are then successively studied at more detailed levels for maximal accuracy. This procedure, implemented and applied to several circuits, is shown to significantly reduce the analysis time.< >

关键词： Timing Delay Circuit analysis computing Very large scale integration Circuit analysis Performance analysis Switches Mathematics computer science Computational modeling

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BOUNDS ON THE ERROR PERFORMANCE OF CODING FOR NONINDEPENDENT RICIAN-FADING CHANNELS

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IEEE TRANSACTIONS ON COMMUNICATIONS 1992年第2期40卷 351-360页

作者： GAGNON, F HACCOUN, D Department of Electrical and Computer Engineering Ecole Polytechnique de Montréal Universite de Montreal Montreal QUE Canada

New upper bounds on the error performance of coded systems for Rician channels are presented. The fading channels need not be fully interleaved to obtain meaningful performance results. These bounds hold for coherent, differentially coherent and noncoherent demodulation of binary signals. They provide a useful analytical approach to the evaluation of the error performance of convolutional or block coding and they may be generalized to M-ary signals and trellis modulation. The approach allows for complex bounds using the fine structure of the code, for simpler bounds similar to those on memoryless channels and finally for a random coding bound using the cutoff rate of the channel. The analysis thus permits a step by step evaluation of coded error performances for Rician-fading channels.

关键词： Performance analysis Upper bound Rician channels Fading Demodulation Signal analysis Convolutional codes Convolution Block codes Modulation coding

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SOURCE-PULL LOAD-PULL OSCILLATOR MEASUREMENTS AT MICROWAVE MM WAVE FREQUENCIES

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 1992年第1期41卷 32-35页

作者： GHANNOUCHI, FM BOSISIO, RG The Microwave Research Laboratory Electrical and Computer Engineering Department Ecole Polytechnique de Montreal Montreal QUE Canada

A six-port reflectometer with variable test port impedance over 2-6 GHz was designed, built, and tested. The potential use of this reflectometer is in large signal characterization of negative resistance devices and oscillators. Experimental source-pull/load-pull measurements on a commercial oscillator (Rieke Diagram) were performed using this reflectometer over the entire Smith chart.

关键词： Microwave oscillators Microwave measurements Frequency measurement Electrical resistance measurement Impedance measurement Q measurement Microwave devices Scattering parameters System testing Tuners

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AN AUTOMATED MILLIMETER-WAVE ACTIVE LOAD-PULL MEASUREMENT SYSTEM BASED ON 6-PORT TECHNIQUES

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 1992年第6期41卷 957-962页

作者： GHANNOUCHI, FM BOSISIO, RG Microwave Research Laboratory Electrical and Computer Engineering Department Ecole Polytechnique de Montrèal Montreal QUE Canada

This paper presents a millimeter-wave active load-pull measurement system for large-signal characterization of millimeter-wave transistors. The characterization system uses two six-port junctions for simultaneous impedance and power flow measurements. Large-signal characterization of a GaAs FET operated in class A and class C at 28 GHz in terms of constant absorbed power contours, constant operating power gain contours and constant DC current contours in the load plane Z(L) is presented. Effects of the unilaterality assumption on the operating power gain and output power are investigated for both class A and class C amplifier designs.

关键词： Millimeter wave measurements Millimeter wave transistors Power amplifiers Load flow Impedance measurement Power measurement Fluid flow measurement Gallium arsenide FETs Power generation

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RELATIVE-CLOCK-BASED SPECIFICATION AND TEST RESULT ANALYSIS OF DISTRIBUTED SYSTEMS 11

RELATIVE-CLOCK-BASED SPECIFICATION AND TEST RESULT ANALYSIS ...

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11TH ANNUAL INTERNATIONAL PHOENIX CONF ON computerS AND COMMUNICATIONS ( IPCCC-92 )

作者： PROBERT, RL YU, HL SALEH, K Protocol and Software Engineering Research Group Department of Computer Science University of Ottawa Ottawa K1N6N5 ON Canada Department of Electrical and Computer Engineering Concordia Urrrversity Montreal Canada

ISBN: (纸本)0780306058

A model employing totally ordered events of a distributed system based on a logical clock has been presented by L. Lamport (1978). The authors propose a new interpretation and extension of Lamport's notion of concurrency by introducing the concept of relative concurrency to capture the nature of concurrency of distributed systems by means of a relative (or logical) clock. They then derive a totally ordered global events model based on the relative clock. Based on this model, they represent and interpret timing (ordering) information from observable scenarios, including collision scenarios of the system, expressed in an extended trace assertion language (ETAL) specification. Finally, a new approach is illustrated with a realistic example for test result analysis including timing information based on the global events model. © 1992 IEEE.

关键词： DISTRIBUTED SYSTEMS FORMAL SPECIFICATIONS RELATIVE CONCURRENCY LOCAL GLOBAL EVENTS RELATIVE CLOCK TIME TOTAL ORDER OF EVENTS TEST RESULT ANALYSIS software TESTABILITY

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Communication load and delay in multichannel land mobile systems for dispatch traffic: A queueing analysis

Communication load and delay in multichannel land mobile sys...

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IEEE Conference on Vehicular Technology (VTC)

作者： H.H. Hoang R. Malhame C. Rosenberg Department of Electrical and Computer Engineering École Polytechnique Montreal QUE Canada

Methods for analysis of land mobile radio trunked systems with dispatch traffic were investigated. A queuing model is proposed to take into account fleet delays, which occur when mobile operators must wait because their own dispatchers are busy with a call. A decomposition approach is applied to solve the model using well-known queuing results. Once the distribution of central delays due to channel sharing is known, fleet delays are computed by means of an M/G/1 model with finite population. For trunked systems supporting a large number of fleets, the analysis of central delays is performed using the G/H/sub 2//s queue. When the number of fleets is not much greater than the number of channels, channel sharing delays must be analyzed by means of a multiserver queue with finite population. Simulations are used to validate the decomposition approach. The results obtained show that besides depending on the communication load, the grade of service of trunked systems also depends on the size of fleets.< >

关键词： Mobile communication Delay Traffic control Land mobile radio Queueing analysis Privacy Fires Distributed computing Performance analysis Radio frequency

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Bidirectional decoding of convolutional codes for wide-band TDMA indoor wireless channels

Bidirectional decoding of convolutional codes for wide-band ...

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IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： C.L. Despins J. Belzile D. Haccoun Department of Electrical and Computer Engineering Ecole Polytechnique de Montrèal Montreal QUE Canada

Bidirectional suboptimal breadth-first decoding of convolutional codes is an attractive technique for slowly-varying and quasistatic fading channels as it restricts the extent of decoding errors due to correct path loss to very heavy noise or interference regions. The paper compares the performance of such a decoding scheme to the Viterbi algorithm over wideband TDMA indoor radio links where equalization and space diversity are also used to combat dispersive fading and cochannel interference. It is shown that, with dual space diversity, Viterbi decoding and bidirectional decoding of convolutional codes are both attractive alternatives, in terms of outage rate, to increasing the space diversity order from two to three. On the basis of equal computational complexity, bidirectional decoding is also shown to be superior to Viterbi decoding. Furthermore, this advantage increases as the bit error rate performance criterion becomes more stringent which makes bidirectional decoding particularly attractive for data applications.< >

关键词： Decoding Convolutional codes Wideband Time division multiple access Viterbi algorithm Fading Error correction codes Interference Indoor radio communication Dispersion

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A New Variable Testability Measure: a Concept for Data-Flow Testability Evaluation

A New Variable Testability Measure: a Concept for Data-Flow ...

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International Conference on VLSI Design

作者： M. Jamoussi B. Kaminaka D. Mukhedkar Department of Electrical and Computer Engineering Ecole Polytechnique de Montrèal Montreal QUE Canada

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Relative-clock-based specification and test result analysis of distributed systems

Relative-clock-based specification and test result analysis ...

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International Phoenix Conference on computers and Communications (IPCCC)

作者： R.L. Probert H. Yu K. Saleh Department of Computer Science Protocol and Software Engineering Research Group University of Ottawa Ottawa ONT Canada Department of Electrical and Computer Engineering Concordia University Montreal Canada

关键词： System testing Clocks software testing Concurrent computing Timing Information analysis Protocols software engineering computer science Formal specifications

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Test quality of hierarchical defect-tolerant integrated circuits

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Journal of Electronic Testing 1992年第1期3卷 93-102页

作者： Thibeault, Claude Savaria, Yvon Houle, Jean-Louis Computer Science Department U.Q.A.M. Montreal H3C 3P8 QC C.P. 8888 Station A Canada Electrical Engineering Department Ecole Polytechnique de Montréal Montreal H3C 3A7 QC C.P. 6079 Station A Canada

This paper presents a theoretical expression to evaluate the test quality of hierarchical defect-tolerant integrated circuits. This expression, which is developed for circuits with two levels of hierarchy, is based on a defect model with which one can take into account the relative importance (probability of occurrence) of each defect and consequently of each fault. Results obtained from this expression show that, for a given test coverage, the addition of defect-tolerance mechanisms decreases the test quality of integrated circuits. These results are important because they indicate that fault coverage can be a misleading measure of the test quality of defect-tolerant integrated circuits. © 1992 Kluwer Academic Publishers.

关键词： Combinatorial analysis defect level defect modeling defect tolerance fault coverage

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