Students of today are immersed in the culture of mobile technology and the laptop has become a center of connectivity to their world around them, and its use a fundamental means of social and academic success. This wi...
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An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates fou...
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In the near future mobile robots accomplishing such tasks as delivery of goods, assistance for handicapped people and surveillance will become increasingly available. The aim of this paper is to show the disparity tha...
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An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates fou...
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ISBN:
(纸本)9781424438273
An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates four-phase clocks and synchronizes the reference clock with the output clock within 45 cycles. Furthermore, the clock generator uses a fine binary scheme and de-skewing circuit for fine delay measurement and compensation. The proposed clock generator was designed in a 0.18 mum CMOS technology. It operates over a wide frequency range from 400 MHz to 1.22 GHz and consumes 34 mW at 1.22 GHz.
It is an exciting time to be in television. The advances in digital television, computers, and all the peripherals related to them open the creative gate for television graphic designers. Television is undergoing some...
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It is an exciting time to be in television. The advances in digital television, computers, and all the peripherals related to them open the creative gate for television graphic designers. Television is undergoing some growing pains and is about to transform into an entirely new format.
A wide-range low-jitter digital DLL using 0.18 um single-poly four-metal CMOS technology is proposed that uses an open-loop time-to-digital converter (TDC)-based DCC circuit with 10 cycles of maximum locking time by v...
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A wide-range low-jitter digital DLL using 0.18 um single-poly four-metal CMOS technology is proposed that uses an open-loop time-to-digital converter (TDC)-based DCC circuit with 10 cycles of maximum locking time by virtue of pulse width detection scheme. In addition, the DLL uses a semi dual delay line to remove the boundary switching problem and to optimize its area and power consumption. Thus, the proposed DLL operates over a frequency range from 170 MHz to 1.4 GHz. The peak-to-peak jitter is 13.8 ps at 1.4 GHz and the power consumption is reduced to 27 mW.
Based on Catmull-Clark Subdivision scheme, a valid algorithm of offset approximation for Subdivision Surface is proposed. It can overcome the defect that previous approaches treat offset surface only as parametric sur...
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Using the concept of duality between points and planes in 3D projective space, an explicit and efficient method of computer-aided design for developable surfaces based on Bezier and B-spline basis functions is propose...
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Story board creation can be an alternative way of teaching visual problem solving. Expressing a concept or idea showing action, or thinking a problem through from start to finish can be done through storyboards. The v...
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