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Channel Width Utilization Improvement in Testing NoC-Based systems for Test Time Reduction

Channel Width Utilization Improvement in Testing NoC-Based S...

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Jia Li Qiang Xu Yu Hu Xiaowei Li Key Laboratory of Computer System and Architecture ICT CAS Beijing China Department of Computer Science & Engineering Chinese University of Hong Kong Hong Kong China Chinese Academy and Sciences Beijing China

Testing NoC-based systems mainly relies on reusing the Network-on-Chip architecture as the test access mechanism (TAM). This, however, implies that the core's test wrapper is supplied with full NoC channel width even if there is a mismatch between the two. How to effectively and efficiently make better utilization of the NoC channels for test data transferring is therefore an interesting and challenging problem. In this paper, we propose to combine a new wrapper design with interleaved test scheduling. Compared to [8], the proposed method can achieve better NoC channel utilization for test without manipulating test frequencies, which not only reduces test power, but also saves design effort for the test engineers. Consequently, the testing time of the NoC-based system is considerably reduced with the proposed technique (especially under stringent power constraints), as shown in the experimental results on circuits crafted from ITC02 benchmarks.

关键词： system testing Network-on-a-chip Circuit testing system-on-a-chip Electronic equipment testing Frequency Logic testing Clocks Application software Content addressable storage

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Advanced QoS methods for Grid workflows based on meta-negotiations and SLA-mappings

Advanced QoS methods for Grid workflows based on meta-negoti...

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Workshop on Workflows in Support of Large-Scale science, WORKS

作者： Ivona Brandic Dejan Music Schahram Dustdar Srikumar Venugopal Rajkumar Buyya Institute of Information Systems University of Technology Vienna Austria Grid Computing and Distributed System (GRIDS) Laboratory Department of Computer Science and Software Engineering University of Melbourne Australia

In novel market-oriented resource sharing models, resource consumers pay for the resource usage and expect that non-functional requirements for the application execution, termed as quality of service (QoS), are satisfied. QoS is negotiated between two parties following the specific negotiation protocols and is recorded using service level agreements (SLAs). However, most of the existing work assumes that the communication partners know about the SLA negotiation protocols and about the SLA templates before entering the negotiation. However, this is a contradictory assumption, if we consider computational grids and novel, commercially oriented computing clouds where consumers and providers meet each other dynamically. In this paper, we present novel meta-negotiation and SLA-mapping solutions for grid workflows bridging the gap between current QoS models and grid workflows, one of the most successful grid programming paradigms. We illustrate the open research issues with a real world case study. Thereafter, we present document models for the specification of meta-negotiations and SLA-mappings. We discuss the architecture for the management of meta-negotiations and SLA-mappings as well as integration of the architecture into a grid workflow management framework.

关键词： Quality of service Protocols Grid computing Cloud computing Resource management Information systems Laboratories computer science Software engineering Application software

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Application of Advanced Process Control in Plastic Injection Molding

Application of Advanced Process Control in Plastic Injection...

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2008 IEEE International Conference on Service Operations and Logistics, and Informatics(IEEE/SOLI’2008)(IEEE服务运作、物流与信息年会)

作者： Juhn-Horng Chen Long-Jye Sheu Wen-Chin Chen Hsien-Keng Chen Chen-Tai Chen Department of Mechanical EngineeringChung Hua UniversityHsinchu Chinese Taipei Department of Industrial Engineering and System ManagementChung Hua UniversityHsinchu Chinese Taipei Department of Industrial Engineering and ManagementHsiuping Institute of TechnologyTaichung Chinese Department of Computer Science and Information Engineering Ta Hwa Institute of Technology Hsinchu Ch

This research applies Advanced Process Control (APC)-based injection molding system to improve the quality of *** relationships between the input parameters (injection velocity,injection pressure,injection time and barrel temperature) and a single output variable (the weight of product) were found through an experimental design ***,the injection molding process model was built via a multiple regression analysis.A dynamic model turning minimum variance (DMTMV) method is utilized to control the *** improvements were further obtained from experiments.

关键词： advanced process control design of experiment injection molding dynamic model turning minimum variance

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Which Spot Should I Test for Effective Embedded Software Testing?

Which Spot Should I Test for Effective Embedded Software Tes...

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International Conference on Secure system Integration and Reliability Improvement, SSIRI

作者： Jooyoung Seo Yuhoon Ki Byoungju Choi Kwanghyun La Department of Computer Science and Engineering Ewha University Seoul South Korea Mobile Solution System LSI Division Samsung Electronics Company Limited Yongin si South Korea

ISBN: (纸本)9780769532660

Today, the embedded industry is changing fast - systems have become larger, more complex, and more integrated. Embedded system consists of heterogeneous layers such as hardware, HAL, device driver, OS kernel, and application. These heterogeneous layers are usually customized for special purpose hardware. Therefore, various hardware and software components of embedded system are mostly integrated together under unstable status. That is, there are more possibilities of faults in all layers unlike package *** this paper, we propose the embedded software interface as two essential parts: interface function that represents the statement of communication between heterogeneous layers, and interface variable that represents software and/or hardware variable which are defined in different layer from integrated software and used to expected output for decision of fault. Also, we statically investigate various views of embedded software interface and demonstrate that proposed interface should be new criterion for effective embedded software testing.

关键词： Software Hardware Testing Complexity theory Software measurement system software Embedded system

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Block remap with turnoff: A variation-tolerant cache design technique

Block remap with turnoff: A variation-tolerant cache design ...

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Asia and South Pacific Design Automation Conference

作者： Mohammed Abid Hussain Madhu Mutyam Center for VLSI and Embedded System Technologies International Institute of Information Technology Hyderabad Hyderabad India Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai India

ISBN: (纸本)9781424419210;1424419212

With reducing feature size, the effects of process variations are becoming more and more predominant. Memory components such as on-chip caches are more susceptible to such variations because of high density and small sized transistors present in them. Process variations can result in high access latency and leakage energy dissipation. This may lead to a functionally correct chip being rejected, resulting in reduced chip yield. In this paper, by considering a process variation affected on-chip data cache, we first analyze performance loss due to worst-case design techniques such as accessing the entire cache with the worst-case access latency or turning off the process variation affected cache blocks, and show that the worst-case design techniques result in significant performance loss and/or high leakage energy. Then by exploiting the fact that not all applications require full associativity at set-level, we propose a variation-tolerant design technique, namely, block remap with turnoff (BRT), to minimize performance loss and leakage energy consumption. In BRT technique we selectively turnoff few blocks after rearranging them in such a way that all sets get almost equal number of process variation affected blocks. By turning off process variation affected blocks of a set, leakage energy can be minimized and the set can be accessed with low latency at the cost of reduced set associativity. We validate our technique by running SPEC2000 CPU benchmark-suite on Simplescalar simulator and show that our technique significantly reduces the performance loss and leakage energy consumption due to process variations.

关键词： Delay Performance loss Energy consumption Turning Costs Central Processing Unit Very large scale integration Embedded system Information technology computer science

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On reducing both shift and capture power for scan-based testing

On reducing both shift and capture power for scan-based test...

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Asia and South Pacific Design Automation Conference

作者： Jia Li Qiang Xu Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong China Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424419210

Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-fllling technique to reduce both shift power and capture power during scan tests, namely LSC-filling . The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT's average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed methodology.

关键词： Circuit testing Energy consumption Power dissipation system testing Electrical fault detection Fault detection Circuit faults Benchmark testing Laboratories Power engineering computing

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Distributed amplifier using enhancement-mode AlGaN/GaN HEMTs

Distributed amplifier using enhancement-mode AlGaN/GaN HEMTs

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International Conference on Communications, Circuits and systems (ICCCAS)

作者： Zhiqun Cheng Xiaopeng Zhou Kevin J. Chen Key laboratory of RF Circuit and System Hangzhou Dianzi University Hangzhou China Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Kowloon Hong Kong China

Distributed amplifiers (DAs) using 1mm-gate enhancement-mode AlGaN/GaN HEMT were designed and fabricated. Design process and simulation results of the DA are given. Simulation results show the input and output VSWR (voltage standing wave ratio) of less than 2, associated gain of more than 8.5dB and gain ripple of less than 1dB at frequency from 2GHz to 6GHz.

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An Optical External Localization system and Applications to Indoor Tracking

An Optical External Localization System and Applications to ...

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2008 IEEE/RSJ International Conference on Intelligent Robots and systems

作者： Linga Srujan Roy Binayak Harry Asada Daniela Rus Computer Science and Artifical Intelligence Laboratory MIT Anna University Cambridge MA USA Department of Mechanical Engineering MIT Arbeloff Laboratory for Information System and Technology Cambridge MA USA

Precise robot positioning is important for many applications in indoor environments. Current solutions to the indoor localization problem are either both unreliable and inaccurate, or very expensive. In this paper we propose, design and build a low-cost, robust and accurate indoor localization system using laser light sources. The system calculates the coordinates of a robotic arm by using triangulation algorithms with precisely measured values of the angles of the receiver with respect to the three laser emitters. A system of three rotating lasers and receiver unit was built and deployed in the wing of an aircraft. Using this system, a robotic arm could be localized accurately within error margins defined approximately by Gaussian distributions centered at the objectpsilas true coordinate values and with standard deviations of 0.19 mm, 0.11 mm and 0.34 mm in the x, y and z coordinate directions respectively. The system was also used to detect vertical drop in the robotic arm due to its weight as it extends to perform fitting operations on the skin of the wing. Feedback from the laser localization system was used to adjust the position of the tip of the robotic arm in order to perform a sequence of high precision docking tasks within the aircraft wing.

关键词： Receivers Measurement by laser beam Robots Robot kinematics Surface emitting lasers Laser beams Transmitters

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Plasma oscillations in field-effect transistor arrays

Plasma oscillations in field-effect transistor arrays

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International Conference on Mathematical Methods in Electromagnetic Theory (MMET)

作者： V.V. Popov D.V. Fateev M.S. Shur Saratov Branch Russian Academy of Science Saratov Russia Department of Electrical Computer and System Engineering and Center for Integrated Electronics CII 9015 Rensselaer Polytechnic Institute Troy NY USA

Terahertz (THz) plasmonic spectra of field-effect transistor (FET) arrays are discussed for two different types of FET arrays: (i) FET array with a common channel and a large-area grating gate, and (ii) array of FET units with separate channels and combined intrinsic source and drain contacts. It is shown that the coupling between plasmons and THz radiation in the FET array can be strongly enhanced as compared to a single-unit FET due to excitation of the cooperative plasmon mode distributed over the entire area of the FET array. The higher-order plasmon modes revealing the plasmon resonances at frequencies up to 20 THz can be excited much more effectively in the array of FET units with separate channels and combined source and drain contacts.

关键词： Plasmons FETs Logic gates Gratings Oscillators Electromagnetics Plasmas

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Generation of random channel specifications for channel routing problem

Generation of random channel specifications for channel rout...

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11th International Conference on computer and Information Technology, ICCIT 2008

作者： Pal, Achira Mandal, Tarak N. Datta, Alak K. Kundu, Debojit Pal, Rajat K. Kolkata: 700 148 West Bengal India IBM India Pvt. Ltd. DLF IT Park New Town PO: Rajarhat Kolkata: 700 156 India Department of Computer and System Sciences Visva-Bharati Santiniketan: 731 235 Birbhum West Bengal India HCL Technologies Ltd. Noida: 201 301 Uttar Pradesh India Department of Computer Science and Engineering University of Calcutta 92 A. P. C. Road Kolkata: 700009 India

ISBN: (纸本)9781424421367

In this paper we develop algorithms for generating random channel specifications of channel routing problem in VLSI design. A channel is a rectangular routing region containing two sets of fixed terminals on two of its opposite sides and the other two opposite sides (of the rectangle) are open ends, mayor may not contain any terminal of a net but the terminal position is not fixed before a routing solution is computed. Most of the problems in two-, three-, and multi-layer channel routing are beyond polynomial time computable. Hence for each of these problems it is unlikely to design a polynomial time deterministic algorithm. Developing heuristic algorithm might be a probable way out that hopefully provides good solutions for most of the instances occur in practice. Novelty of a heuristic algorithm is judged better if it works for a variety of large number of randomly generated instances of the problem. In fact, convergence of results of a heuristic algorithm is well established when the algorithm of a problem is executed for a huge number of randomly generated similar instances and the final result is computed making an average on all of them. ©2008 IEEE.

关键词： Specifications

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