We present a fast incremental algorithm for constructing minimal DFCA for a given language. Since it was shown that the DFCA for a language L can have less states than the DFA for L, this technique seems to be the bes...
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This work describes the interface design and interaction of a generic annotation service for Digital Library Management Systems (DLMSs), called Digital Library Annotation Service (DilaS), that has been designed and is...
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ISBN:
(纸本)1595933530
This work describes the interface design and interaction of a generic annotation service for Digital Library Management Systems (DLMSs), called Digital Library Annotation Service (DilaS), that has been designed and is currently undergoing development and user test in the framework of the DELOS European Network of Excellence. The objective of DilaS is to design and develop an architecture and a framework able to support and evaluate a generic annotation service, i.e. a service that can be easily used into different DLMSs enhancing their User Interfaces (UIs) in order to offer to Digital Library (DL) users a set of uniform, user-tested (under certain required conditions), and recognizable functionalities. Copyright 2006 ACM.
Coalition is an important way of cooperation for multi-agent system. To maximize the summation of the coalition values, and to search for an optimized coalition structure in a minimal searching range, a coalition stru...
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Coalition is an important way of cooperation for multi-agent system. To maximize the summation of the coalition values, and to search for an optimized coalition structure in a minimal searching range, a coalition structure optimization algorithm in multi-agent systems based on particle swarm algorithm (PSO) is proposed. A comparison is made between the operation performances of generic algorithm (GA) and particle swarm optimization in this matter through simulation experiment. The result of the simulation shows the effectiveness of the PSO algorithm
As power dissipation inexorably becomes the major bottleneck in system integration and reliability, the front-end instruction delivery path in a traditional out-of-order superscalar-processor needs to deliver high app...
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ISBN:
(纸本)9781509030224
As power dissipation inexorably becomes the major bottleneck in system integration and reliability, the front-end instruction delivery path in a traditional out-of-order superscalar-processor needs to deliver high application performance in an energy-effective manner. This challenge can be addressed by efficiently reusing the work of fetch and decode performed during preceding loop iterations and resident mostly within the processor itself. As a large percentage of the instructions currently under fetch have previously dispatched copies resident in the Reorder Buffer (ROB), in this paper we develop a mechanism to utilize the ROB as a storage location for previously decoded instructions. Thus instructions can be fed directly from the ROB into the rename and issue stages, enabling the gating off of the fetch and decode logic for large periods of time so as to deliver significant power savings. Power and performance criticality of the ROB requires an efficient reuse identification mechanism; we outline such a cost-efficient Reuse Identification Unit (RIU) which enables effective identification of the matches between the ROB entries and the instructions currently under fetch. Simulation results on both multimedia and SPEC 2000 benchmarks confirm that incorporating the proposed technique on traditional out-of-order superscalar processors results in not only a sight improvement in performance, but also significant savings in the overall system power dissipation, achieved within a limited hardware budget.
Boolean expressions are widely used to model decisions or conditions of a specification or source program. The MUMCUT, which is designed to detect seven common faults where Boolean expressions under test are assumed t...
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Boolean expressions are widely used to model decisions or conditions of a specification or source program. The MUMCUT, which is designed to detect seven common faults where Boolean expressions under test are assumed to be in Irredundant Disjunctive Normal Form (IDNF), is an efficient fault-based test case selection strategy in terms of the fault-detection capacity and the size of selected test suite. Following up our previous work that reported the fault-detection capacity of the MUMCUT when it is applied to general form Boolean expressions, in this paper we present the characteristic of the types of single faults committed in general Boolean expressions that a MUMCUT test suite fails to detect, analyze the certainty why a MUMCUT test suite fails to detect these types of undetected faults, and provide some extensions to enhance the detection capacity of the MUMCUT for these types of undetected faults.
This paper introduces a novel geometry-based simulation technique for the arbitrary indoor OFDM quality-of-service (QoS) analysis. This automatic geometry-driven approach integrates electromagnetic radio propagation m...
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This paper introduces a novel geometry-based simulation technique for the arbitrary indoor OFDM quality-of-service (QoS) analysis. This automatic geometry-driven approach integrates electromagnetic radio propagation modeling, channel characterization, and OFDM interference analysis to quantify the indoor OFDM performance through the off-site computer–aided procedures. Essential OFDM quality-of-service measures, such as signal-to-interference ratios (SIR) and bit error rates (BER) can be generated by this new analysis tool. The resulting QoS measure contours can be used by service providers and OFDM communication system designers to quantify the system performance and determine the optimal accessing locations for any indoor geometry.
This paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. Conventional multiprocessor scheduling, applied to this architecture, will at...
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This paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. Conventional multiprocessor scheduling, applied to this architecture, will attempt to balance the thread load across cores. This research demonstrates that such an approach eliminates one of the big advantages of this architecture - the ability to use unbalanced schedules to allocate the right amount of execution resources to each thread. However, accommodating unbalanced schedules creates several difficulties, the biggest being the fact that the search space of all schedules (both balanced and unbalanced) is much greater than that of the balanced schedules alone. This work proposes and evaluates scheduling policies that allow the system to identify and migrate toward good thread schedules, whether the best schedules are balanced or unbalanced
As there is a lack of central management in an e-commerce interaction carried out based on peer-to-peer architecture, it is obvious for the trusting peer to analyze the risk beforehand that could be involved in dealin...
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As there is a lack of central management in an e-commerce interaction carried out based on peer-to-peer architecture, it is obvious for the trusting peer to analyze the risk beforehand that could be involved in dealing with a trusted peer in these types of interactions. Another characteristic of peer-to-peer architecture interactions is that the trusting peer might have to choose a peer to interact with, from a set of possible trusted peers. It can ease its decision making process of choosing a peer to interact with by analyzing the risk that could be involved in dealing with each of the possible trusted peers. In this paper we highlight and propose a solution to this problem by which the trusting peer can decide with which peer to interact with after analyzing the risk that could be associated in dealing with each of them
We present in this paper a general-purpose approach for articulated object recognition. We split the recognition process in two distinct phases. In the former we use standard model-based techniques in order to recogni...
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We present in this paper a general-purpose approach for articulated object recognition. We split the recognition process in two distinct phases. In the former we use standard model-based techniques in order to recognize and localize in the input image the rigid components the articulated object is composed of. In the second phase the spatial configurations formed by the recognized components are analyzed and compared with the valid configurations of the object we are searching. The comparison is based on a constraint satisfaction method which can deal with both missing components and false positives. The proposed method is based on a redundant set of constraints which represent the valid spatial configurations of the object's components. Such constraints are not embedded in the system nor are domain-specific but they are learned during a suitable training phase. We show how this approach can be used in different scenarios with different kinds of articulated objects and we present a case study concerning a robotic application.
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