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IJCNN International Joint Conference on Neural Networks

作者： Suresh S.Kalkunte J.Mohan Kumar L.M.Patnaik Microprocessor Applications Laboratory Indian Institute of Science Microprocessor Applications Laboratory Supercomputer Education and Research Centre Dept. of Computer Science and Automation Indian Institute of Science

Locating faults is an essential procedure to be carried out during the design,fabrication and operational phases of a digital *** faults using the conventional method,requires a search through the fault dictionary for the appropriate fault *** time taken to search using a search tree is prohibitively *** important feature of Adaptive Resonance Theory(ART-l) network,a neural network paradigm,where stable learnt codes are accessed instantaneously,is used to our advantage to locate faults in digital *** this paper,we discuss the implementation of the ART-1 network to detect faults in digital *** ART networks are employed to learn the faulty output and the corresponding input *** faulty output patterns being saved in the ART-1 network are accessed instantaneously,thus considerably reducing the time taken to locate *** reduction in the fault locating time is attributed to the rejection of repeatedly occurring input and output patterns by an ART-1 network.

关键词： Diagnostic resolution Attentional subsystem Orienting subsystem Pseudo-Random patterns Fault location

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ROBOTIC PATH CONTROL USING BACKPROPAGATION NETWORK ON A TRANSPUTER SYSTEM

ROBOTIC PATH CONTROL USING BACKPROPAGATION NETWORK ON A TRAN...

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IJCNN International Joint Conference on Neural Networks

作者： T.J.Bninda J.Mohan Kumar L.M.Patnaik Microprocessor Applications Laboratory Microprocessor Applications Laboratory Supercomputer Education and Research Centre Dept.of Computer Science and Automation Indian Institute of Science Bangalore 560 012INDIA

＜正＞A neural network based controller for a typical robotic application such as path control is presented in this *** learning is incorporated into the control loop for controlling the movement of a robot arm with single degree of *** meet the real-time requirements of robotic control problem,we have implemented the backpropagation algorithm on a transputer *** obtained indicate that backpropagation algorithm implemented on a transputer system yields response times of the order of milliseconds.

关键词： Artificial Neural Networks Backpropagation Algorithm Robotic Path Control Transputers ’

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A Force Directed Hill-Climbing Placement Algorithm

A Force Directed Hill-Climbing Placement Algorithm

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International Conference on VLSI Design

作者： R. Mall L.M. Patnaik Department of Computer Science and Automation Indian Institute of Science Bangalore India Microprocessor Applications Laboratory Indian Institute of Science Bangalore India

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Performability studies of hypercube architectures

Performability studies of hypercube architectures

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International Symposium on Parallel Processing

作者： S.M. Koriem L.M. Patnaik Department of Computer Science and Automation Indian Institute of Science Bangalore India Microprocessor Applications Laboratory Indian Institute of Science Bangalore India

The authors propose a novel technique to study composite reliability and performance (performability) measures of hypercube systems using generalized stochastic Petri nets (GSPNs). This technique essentially consists of the following: (i) a GSPN reliability model; (ii) a GSPN performance model; and (iii) a way of combining the results from these two models. Models and performability results for an iPSC/2 hypercube system under the workload of concurrent matrix multiplication algorithm are presented.< >

关键词： Hypercubes Performance analysis Video recording computer architecture Performance evaluation Stochastic processes Petri nets Steady-state Hardware microprocessors

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T-algorithm-based logic simulation on distributed systems

T-algorithm-based logic simulation on distributed systems

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Great Lakes Symposium on VLSI

作者： S. Sundaram L.M. Patnaik Computer Aided Design Laboratory Supercomputer Education & Research Centre Indian Institute of Science Bangalore India Microprocessor Application Labortory Supercomputer Educatiori & Research Centre Department of Computer Science and Automation Indian Institute of Science Bangalore India

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic simulation algorithms is by exploiting the inherent parallelism in the sequential version. The authors explore the possibility of mapping a T-algorithm based logic simulation algorithm onto a cluster of workstations interconnected by an Ethernet. The set of gates at a particular level is partitioned by the master task (running on the host processor) among the slave tasks (running on the other processors). Each slave task evaluates the set of gates assigned to it, for the complete simulation period independent of other slave tasks and communicates the evaluated outputs to the master task. After receiving the evaluated output from all the slaves, the master task partitions the gates at the next level and communicates this new set of gates to the slave tasks. The above process is repeated for all the levels in the circuit. The details of the partitioning scheme and its performance are also discussed.< >

关键词： Circuit simulation Master-slave Clustering algorithms Partitioning algorithms Very large scale integration Digital circuits Logic design Logic circuits Workstations Integrated circuit interconnections

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Unlearning in feed-forward neural networks

Unlearning in feed-forward neural networks

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1991 IEEE Region 10 International Conference on EC3-Energy, computer, Communication and Control Systems, TENCON 1991

作者： Venkatesh, T.G. Patnaik, L.M. Department of Computer Science and Automation Indian Institute of Science Microprocessor Applications Laboratory Bangalore560012 India Supercomputer Education and Research Centre Department of Computer Science and Automation Indian Institute of Science Bangalore560012 India

ISBN: (纸本)0780305388

We present two algorithms for unlearning an already stored pattern in feed- forward neural networks. The proposed algorithms are modifications of the backpropagation method. The method will find applications whenever the training set has to be updated frequently. The proposed algorithms have the propery that the retrieval of other pattens are not affected due to the selective unlearning. © 1991 IEEE.

关键词： Feedforward neural networks

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OR-parallel evaluation of logic programs on a multi-ring dataflow machine

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New Generation Computing 1991年第1期10卷 23-53页

作者： Sastry, A.V.S. Patnaik, L.M. Department of Computer and Information Science University of Oregon Eugene 97403 OR United States Microprocessor Applications Laboratory Indian Institute of Science Bangalore 560012 India

Logic programming languages have gained wide acceptance because of two reasons. First is their clear declarative semantics and the second is the wide scope for parallelism they provide which can be exploited by building suitable parallel architectures. In this paper, we propose a multi-ring dataflow machine to support the OR-parallelism and the Argument parallelism of logic programs. A new scheme is suggested for handling the deferred read mechanism of the dataflow architecture. The required data structures, the dataflow actors and the builtin dataflow procedures for OR-parallel execution are discussed. Multiple binding environments arising in the OR-parallel execution are handled by a new scheme called the tagged variable scheme. Schemes for constrained OR-parallel execution are also discussed. © 1991 Ohmsha, Ltd. and Springer.

关键词： Dataflow Model Logic Programming OR-Parallelism Resolution Unification

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A new approach to specify real-time behavior of distributed systems

A new approach to specify real-time behavior of distributed ...

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1991 Pacific Rim International Symposium on Fault Tolerant Systems, RFTS 1991

作者： Mall, R. Patnaik, L.M. Dept. of Computer Science and Automation Indian Institute of Science Bangalore India Microprocessor Applications Laboratory Supercomputer Education and Res. Centre Dept. of Computer Science and Automation Indian Institute of Science Bangalore India

ISBN: (纸本)081862275X

Specification of real-time behavior of a system requires a significantly different approach compared to specification of the system's non-real-time behavior. Also, a specification formalism should be easy to use, conceptually simple, and should lead to an intuitive understanding about the specified behavior of the system. With these objectives, in this paper, we develop an event-based approach to specify the real-time behavior and relevant properties of distributed systems. In our approach, events are considered as the basic entities and a system is specified by constructing various relations among the events. Based on this formalism, a specification language is also presented. A specification in this language can be automatically transformed into equivalent specifications in many existing formalisms (e.g. temporal logic, firstorder logic, etc.) for further analysis. Thus, an eventbased specification can be used as a front-end tool for automatically generating specifications in many existing formalisms, which can save the trouble of writing complicated formulas in those formalisms. © 1991 IEEE.

关键词： Specifications

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An algorithm for discrete event logic simulation on distributed systems

An algorithm for discrete event logic simulation on distribu...

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1991 IEEE Region 10 International Conference on EC3-Energy, computer, Communication and Control Systems, TENCON 1991

作者： Sundaram, S. Mohan, T.S. Patnaik, L.M. Indian Institute of Science Bangalore560 012 India Computer Aided Design Laboratory India Supercomputer Education and Research Centre Knowledge Based Computer System Laboratory India Supercomputer Education and Research Centre Dept. of Computer Science and Automation Microprocessor Applications Laboratory India

ISBN: (纸本)0780305388

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic Simulation Agorithms is by exploiting the inherent parallelism of the sequential version. In this paper, we explore the possibility of mapping an event driven logic simulation algorithm onto a cluster of processors interconnected by an ethernet. The set of events at any simulation time. step is partitionecl by the Master Task (running on the host processor) anlong the Worker Tasks(running of the other processor's). The partitioning scheme ensures a balanced load. Each Worker Task determines the fanout, elementts, evaluates them independently and comes up with the new event list which is passed onto the Master Task. After receiving the event lists from all the workers, the Master Task increments the simulation time step, computes the new event list partition for the next simulation cycle. We have implemented this distributed logic simulation algorithm on a set of 8 VAXstations using CT - A package for distributed programming. The paper concludes with a note on the speedup figures obtained on the ISCAS benchmark circuits. © 1991 IEEE.

关键词： computer circuits

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Simulated annealing-based channel routing on hypercube computers 4

Simulated annealing-based channel routing on hypercube compu...

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4th CSI/IEEE International Symposium on VLSI Design, VLSI 1991

作者： Mall, R. Patnaik, L.M. Raman, S. Dept. of Computer Science and Automation Microprocessor Applications Laboratory Supercomputer Education and Research Centre Indian Institute of Science Bangalore560012 India Dept. of Electrical and Computer Engineering Coordinated Science Laboratory University of Illinois Urbana-ChampaignIL61801 United States

ISBN: (纸本)0818621257

Many times, routing of signal nets in the layout design of VLSI circuits turns out to be a bottleneck in designing complex chips, due to the inherent compute-intensive nature of this task. Parallel processing of the routing problem holds promise for mitigating this situation. The authors present a parallel channel routing algorithm that is targetted to run on loosely coupled computers like hypercubes. The proposed parallel algorithm employs simulated annealing technique for achieving near-optimum solutions. For efficient execution, attempts have been made to reduce the communication overheads by restricting broadcast of updates only to cases of interprocessor net transfers. Performance evaluation studies on the algorithm show promising results. © 1991 IEEE.

关键词： Simulated annealing

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