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A parallel algorithm for logic simulation on transputer networks 1

A parallel algorithm for logic simulation on transputer netw...

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1st Great Lakes Symposium on VLSI, GLSV 1991

作者： Srinivas, S. Basu, A. Paulraj, A. Patnaik, L.M. Department of Electrical and Computer Engg. Concordia University MontrealQCH3G1M8 Canada Bangalore560025 India Microprocessor Applications Laboratory Supercomputing Education and Research Center Department of Computer Science and Automation Indian Institute of Science Bangalore560012 India

ISBN: (纸本)0818621702

The authors present a parallel algorithm for logic simulation of VLSI circuits. It is implemented on a network of transputers connected in a ring topology. The approach is based on partitioning a functionality matrix representation of the circuit among the transputers and adopting a data flow technique for the solution. A significant aspect of the algorithm is that it overlaps computation with communication, thereby reducing the communication overhead. It also attempts even distribution of load in order to reduce processor idle time. The algorithm possesses the advantages of ease of implementation and ease of extension to incorporate additional parameters for simulation. Performance results of the algorithm are given. © 1991 IEEE.

关键词： Transputers

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A temporal logic over partial orders for analysis of real-time properties of distributed programs

A temporal logic over partial orders for analysis of real-ti...

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1991 IEEE Region 10 International Conference on EC3-Energy, computer, Communication and Control Systems, TENCON 1991

作者： Mall, R. Patnaik, L.M. Supercomputer Education and Research Centre Indian Institute of Science Dept. of Computer Science and Automation Bangalore560 012 India Supercomputer Education and Research Centre Indian Institute of Science Microprocessor Applications Laboratory Bangalore560 012 India

ISBN: (纸本)0780305388

Temporal logic is widely acclaimed to be a highly successful tool for analyzing non-real-time properties of programs. However, a few fundamental problems arise while designing temporal logic-based-techniques to verify real-time properties of programs. in this context, we formulate a modal logic called distribued logic (DL) by using ideas from both the interleaving and partial ordering approach. This logic uses spatial modal operators in addition to temporal operators for representing real-timed concurrency. In addition to the syntax and semantics of the logic, programming model and a formal proof technique based on the logic are also presented. Finally, use of the proof method is illustrated through the analysis of the real-time properties of a generic multiproceess producer/consumer program. © 1991 IEEE.

关键词： Temporal logic

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Associative memory design: Fokker-Planck formalism

Associative memory design: Fokker-Planck formalism

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International Joint Conference on Neural Networks (IJCNN)

作者： T.G. Venkatesh L.M. Patnaik Microprocessor Applications Laboratory Indian Institute of Science Bangalore India Microprocessor Applications Laboratory Supercomputer Education and Research Centre Department of Computer Science and Automation Indian Institute of Science Bangalore India

A design methodology for associative memory (AM) using the Fokker-Planck formalism is proposed. This method allows AM to be designed for noisy conditions by taking into account the noise level to be tolerated by the AM as a design specification. The AM is viewed as a stochastic nonlinear dynamical system governed by a Fokker-Planck equation (FPE). Using eigenfunction expansion the spectrum of the FPE governing the dynamics of the desired AM is derived. A method for designing neural networks having the derived FPE dynamics is also given.< >

关键词： Associative memory Eigenvalues and eigenfunctions Design methodology Nonlinear dynamical systems Noise level Stochastic resonance Nonlinear equations Neural networks Differential equations microprocessors

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Transputer-based parallel systems for performance evaluation of bidirectional associative memory

Transputer-based parallel systems for performance evaluation...

引用

International Joint Conference on Neural Networks (IJCNN)

作者： I. Mahadevan L.M. Patnaik Department of Computer Science and Automation Indian Institute of Science Bangalore India Microprocessor Applications Laboratory Supercomputer Education and Research Centre and Department of Computer Science and Automation Indian Institute of Science Bangalore India

Parallel implementation of an artificial neural network for pattern association, the bidirectional associative memory (BAM), is discussed. Transputer-based parallel architectures like the hypercube, mesh and linear array were used to exploit parallelism in the BAM. A comparative study of utilization and speedup for various architectures was made. The hypercube performed better in terms of utilization and speedup when compared to the other architectures.< >

关键词： Associative memory Magnesium compounds Parallel architectures Hypercubes Parallel processing computer science automation microprocessors Artificial neural networks Bismuth

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Unlearning in Feed-Forward Neural Networks

Unlearning in Feed-Forward Neural Networks

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IEEE Region 10 International Conference TENCON

作者： T.G. Venkatesh L.M. Patnaik Department of Computer Science and Automation Indian Institute of Science Microprocessor Applications Laboratory Bangalore India Department of Computer Science and Automation Indian Institute of Science Supercomputer Education and Research Center Bangalore India

We present two algorithms for unlearning an already stored pattern in feed- forward neural networks. The proposed algorithms are modifications of the backpropagation method. The method will find applications whenever the training set has to be updated frequently. The proposed algorithms have the propery that the retrieval of other pattens are not affected due to the selective unlearning.

关键词： Intelligent networks Feedforward systems Neural networks Feedforward neural networks Neurons Backpropagation algorithms Application software Joining processes microprocessors Supercomputers

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Learning neural network weights using genetic algorithms-improving performance by search-space reduction

Learning neural network weights using genetic algorithms-imp...

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International Joint Conference on Neural Networks (IJCNN)

作者： M. Srinivas L.M. Patnaik Department of Computer Science and Automation Indian Institute of Science Bangalore India Microprocessor Applications Laboratory Supercomputer Education and Research Centre Department of Computer Science and Automation Indian Institute of Science Bangalore India

The authors present a technique for reducing the search-space of the genetic algorithm (GA) to improve its performance in searching for the globally optimal set of connection-weights. They use the notion of equivalent solutions in the search space, and include in the reduced search-space only one solution, called the base solution, from each set of equivalent solutions. The iteration of the GA consists of an additional step where the solutions are mapped to the respective base solutions. Experiments were conducted to compare the performance of the GAs with and without search-space reduction. The experimental results are presented and discussed.< >

关键词： Neural networks Genetic algorithms Neurons computer science automation microprocessors Application software Laboratories Supercomputers computer science education

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A Temporal Logic over Partial Orders for Analysis of Real-Time Properties of Distributed Programs

A Temporal Logic over Partial Orders for Analysis of Real-Ti...

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IEEE Region 10 International Conference TENCON

作者： R. Mall L.M. Patnaik Department of Computer Science and Automation Indian Institute of Technology Bangalore India Microprocessor Applications Laboratory and Supercomputer Education and Research Centre Indian Institute of Technology Bangalore India

关键词： Logic programming Concurrent computing Petri nets Interleaved codes Clocks computer science automation microprocessors Application software Laboratories

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Efficient implementation of bidirectional associative memories on the extended hypercube

Efficient implementation of bidirectional associative memori...

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International Joint Conference on Neural Networks (IJCNN)

作者： J.M. Kumar L.M. Patnaik Microprocessor Applications Laboratory Indian Institute of Science Supercomputer Education and Research Center Bangalore India Department of Computer Science and Automation & Supercomputer Education and Research Center Indian Institute of Science Bangalore India

Implementation of bidirectional associative memories (BAMs) on various multiprocessor topologies is discussed. Studies reveal that BAMs can be implemented efficiently on the extended hypercube (EH) topology since the performance of the extended hypercube is better than that of the binary hypercube topology. The architecture of the BAM network and implementation aspects of BAMs on multiprocessor topologies are discussed. An overview of the EH topology and efficient execution of multinode broadcast and total exchange problems on the EH are considered. Results of the simulation studies are presented.< >

关键词： Hypercubes Neurons Network topology Magnesium compounds Associative memory Computational modeling Broadcasting Artificial neural networks Multiprocessing systems microprocessors

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A parallel algorithm for logic simulation on transputer networks

A parallel algorithm for logic simulation on transputer netw...

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Great Lakes Symposium on VLSI

作者： S. Srinivas A. Basu A. Paulraj L.M. Patnaik Department of Electrical and Computer Engineering Concordia University Montreal QUE Canada Centre for Development of Advanced Computing Bangalore India Microprocessor Applications Laboratory Supercomputing Education and Research Center Department of Computer Science and Automation Indian Institute of Science Bangalore India

关键词： Parallel algorithms Circuit simulation Computational modeling Concurrent computing Application software Logic circuits Very large scale integration Algorithm design and analysis Logic design Design automation

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Simulated annealing-based channel routing on hypercube computers

Simulated annealing-based channel routing on hypercube compu...

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CSI/IEEE International Symposium on VLSI Design

作者： R. Mall L.M. Patnaik S. Raman Department of Computer Science and Automation Indian Institute of Science Bangalore India Department of Computer Science and Automation Mircroprocessor Applications Laboratory Supercomputer Education and Research Centre Indian Institute of Science Bangalore India Department of Electrical and Computer Engineering and Coordinated Science Laboratory University of Illinois Urbana-Champaign IL USA

Many times, routing of signal nets in the layout design of VLSI circuits turns out to be a bottleneck in designing complex chips, due to the inherent compute-intensive nature of this task. Parallel processing of the routing problem holds promise for mitigating this situation. The authors present a parallel channel routing algorithm that is targetted to run on loosely coupled computers like hypercubes. The proposed parallel algorithm employs simulated annealing technique for achieving near-optimum solutions. For efficient execution, attempts have been made to reduce the communication overheads by restricting broadcast of updates only to cases of interprocessor net transfers. Performance evaluation studies on the algorithm show promising results.< >

关键词： Computational modeling computer simulation Simulated annealing Routing Hypercubes Signal design Circuit simulation Very large scale integration Parallel processing Coupling circuits

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