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Numerical simulation of detection response of field effect MOS transistor to modulated terahertz radiation signal

Numerical simulation of detection response of field effect M...

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作者： Wang, Yinglei Yan, Zhifeng Zhu, Jingxuan Lin, Xinnan He, Jin Chan, Mansun Cao, Juncheng Institute of Microelectronics School of Electronic Engineering and Computer Science Peking University Beijing 100871 China Key Laboratory of Integrated Microsystems School of Computer and Information Engineering Peking University Shenzhen Graduate School Shenzhen 518055 China Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Clearwater Bay Kowloon 999077 Hong Kong Shanghai Institute of Microsystem and Information Technology Chinese Academy of Science Shanghai 200050 China

The detector response characteristics of the field effect MOS transistor (MOSFET) to modulated terahertz radiation signal are studied in details in this paper by a numerical simulation method developed from the basic hydrodynamic equations which govern the terahertz signal transport in the MOSFET. The numerical method is used with a universal MOSFET carrier density equation coupled to the basic hydrodynamic equations in a much wider range of operation region of MOSFET terahertz detector to develop the numerical simulation program. The simulation results agree well with the existing theory which is only suitable in the nonresonant region. The developed numerical simulation program is also used to analyze the photoresponse characteristics of the MOSFET detector to modulated terahertz radiation in the resonant region, demonstrating potential application in the detector design and optimization from a MOSFET. Copyright © 2010 American Scientific Publishers. All rights reserved.

关键词： MOSFET devices

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Simple tree pattern matching for trees in the prefix bar notation

Simple tree pattern matching for trees in the prefix bar not...

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Prague Stringology Conference 2010, PSC 2010

作者： Lahoda, Jan Žd'árek, Jan Sun Microsystems Czech V Parku 2308/8 148 00 Praha 4 Czech Republic Department of Theoretical Computer Science Faculty of Information Technology Czech Technical University in Prague Kolejní 550/2 160 00 Prague 6 Czech Republic

ISBN: (纸本)9788001045978

A new pushdown automata based algorithm for searching all occurrences of a tree pattern in a subject tree is presented. The algorithm allows pattern matching with don't care symbols and multiple patterns. A simulation algorithm is also proposed, and practical experimental results are presented. © 2010 Czech Technical University in Prague, Czech Republic.

关键词： Pattern matching

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Analytical subthreshold channel potential model of asymmetric gate underlap gate-all-around MOSFET

Analytical subthreshold channel potential model of asymmetri...

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2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

作者： Wang, Shaodi Guo, Xinjie Zhang, Lining Zhang, Chenfei He, Frank Chan, Mansun Key Laboratory of Integrated Microsystems School of Computer and Information Engineering Peking University Shenzhen Graduate School Shenzhen 518055 China Peking University Shenzhen SOC Key Laboratory Shenzhen 518057 China Department of ECE Hong Kong University of Science and Technology Kowloon Hong Kong

ISBN: (纸本)9781424499977

In this paper an analytic subthreshold potential model for undoped cylindrical gate-all-around (GAA) MOSFET with asymmetric gate underlap is developed. This model is derived by solving the Poisson's equation with the parabolic potential approximation, channel length transformation and conformai mapping. The analytic body center potential solution is presented. Compared with TCAD simulations, the proposed model shows good agreements, with different dimensions of the structure and varied bias conditions. The model here is appropriate for predicting the effect of gate misalignment or asymmetric gate underlap in GAA MOSFETs' design. © 2010 IEEE.

关键词： Poisson equation

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A potential-based analytic model for monocrystalline silicon thin-film transistors on glass substrates

A potential-based analytic model for monocrystalline silicon...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit technology

作者： Wang, Shaodi Zhang, Lining Zhang, Jian Wang, Wenping Wu, Wen Zhang, Xukai Liu, Zhiwei Bian, Wei He, Frank Chan, Mansun Key Laboratory of Integrated Microsystems School of Computer and Information Engineering Peking University Shenzhen Graduate School Shenzhen 518055 China Peking University Shenzhen SOC Key Laboratory Shenzhen 518057 China Department of ECE Hong Kong University of Science and Technology Kowloon Hong Kong

ISBN: (纸本)9781424457984

In this paper a potential based model for monocrystalline silicon thin film transistor (TFT) systems on glass (SOG) substrate from the accumulation to the strong-inversion region is developed. By solving the complete dimensional (1D) Poisson's equation, the potential distribution in the channel is obtained. The analytic drain current is expressed accurately base on the potential solution. Compared with TCAD simulations, the proposed current model shows less than 1.05% errors, with the doping concentrations ranging from 1.5×10 16cm-3 to 1.5×1018cm-3 and different bias conditions. The proposed model is appropriate for precise and quick circuit simulation. ©2010 IEEE.

关键词： Glass

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A customized design of DRAM controller for on-chip 3D DRAM stacking

A customized design of DRAM controller for on-chip 3D DRAM s...

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Custom Integrated Circuits Conference (CICC)

作者： Tao Zhang Kui Wang Yi Feng Xiaodi Song Lian Duan Yuan Xie Xu Cheng Youn-Long Lin Department of Computer Science and Engineering Pennsylvania State University PA USA Peking University Unity Microsystems Technology Company Limited Beijing China Department of Computer Science Peking University Beijing China Computer Science Department National Tsing Hua University Hsinchu Taiwan

To address the “memory wall” challenge, on-chip memory stacking has been proposed as a promising solution. The stacking memory adopts three-dimensional (3D) IC technology, which leverages through-silicon-vias (TSVs) to connect layers, to dramatically reduce the access latency and improve the bandwidth without the constraint of I/O pins. To demonstrate the feasibility of 3D memory stacking, this paper introduces a customized 3D Double-Data-Rate (DDR) SDRAM controller design, which communicates with DRAM layers by TSVs. In addition, we propose a parallel access policy to further improve the performance. The 3D DDR controller is integrated in a 3D stacking System-on-Chip (SoC) architecture, where a high-bandwidth 3D DRAM chip is stacked on the top. The 3D SoC is divided into two logic layers with each having an area of 2.5 × 5.0mm 2 , with a 3-layer 2Gb DRAM stacking. The whole chip has been fabricated in Chartered 130nm low-power process and Tezzaron's 3D bonding technology. The simulation result shows that the on-chip DRAM controller can run as fast as 133MHz and provide 4.25GB/s data bandwidth in a single channel and 8.5GB/s with parallel access policy.

关键词： Three dimensional displays Random access memory System-on-a-chip Stacking Bandwidth computer architecture Registers

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A 3D SoC design for H.264 application with on-chip DRAM stacking

A 3D SoC design for H.264 application with on-chip DRAM stac...

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IEEE International Conference on 3D System Integration, 3DIC

作者： Tao Zhang Kui Wang Yi Feng Yan Chen Qun Li Bing Shao Jing Xie Xiaodi Song Lian Duan Yuan Xie Xu Cheng Youn-Long Lin Department of Computer Science and Engineering Pennsylvania State University PA USA Peking University Unity MicroSystems Technology Company Limited Beijing China Department of Computer Science Peking University Beijing China Computer Science Department National Tsing Hua University Hsinchu Taiwan

Three-dimensional (3D) on-chip memory stacking has been proposed as a promising solution to the “memory wall” challenge with the benefits of low access latency, high data bandwidth, and low power consumption. The stacked memory tiers leverage through-silicon-vias (TSVs) to communicate with logic tiers, and thus dramatically reduce the access latency and improve the data bandwidth without the constraint of I/O pin count. To demonstrate the feasibility of 3D memory stacking, this paper introduces a 3D System-on-Chip (SoC) for H.264 applications that can make use of multiple memory channels offered by 3D integration. Two logic tiers are stacked together with each having an area of 2.5×5.0mm 2 , with a 3-layer 8-channel 3D DRAM stacked on the top. The design flow for this 3D SoC is also presented. The prototype chip has been fabricated with GlobalFoundries' 130nm low-power process and Tezzaron's 3D TSV technology. The 3D implementation shows that the 3D ICs can alleviate the pressure from I/O pin count and allow parallel memory accesses through multiple channels.

关键词： Three dimensional displays Random access memory System-on-a-chip Through-silicon vias Stacking Bonding Bandwidth

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Evaluation of a Performance Model of Lustre File System

Evaluation of a Performance Model of Lustre File System

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ChinaGrid Annual Conference (ChinaGrid)

作者： Tiezhu Zhao Verdi March Shoubin Dong Simon See Guangdong Key Laboratory of Computer Network South China University of Technology Guangzhou China Asia-Pacific Science and Technology Center (APSTC) Sun MicroSystems Inc. Singapore Department of Computer Science National University of Singapore Singapore Department of Mechanical & Aerospace Engineering Nanyang Technological University Singapore

As a large-scale global parallel file system, Lustre file system plays a key role in High Performance Computing (HPC) system, and the potential performance of such systems can be difficult to predict because the potential impact to application performance is not clearly understood. It is important to gain insights into the deliverable Lustre file system IO efficiency. In order to gain a good understanding on what and how to impact the performance of Lustre file system. This paper presents a study on performance evaluation of Lustre file systems and we propose a novel relative performance model to predict overhead under different performance factors. In our previous experiments, we discover that different performance factors have a closed correlation. In order to mining the correlations, we introduce relative performance model to predict performance differences between a pair of Lustre file system equipped with different performance factors. On average, relative model can predict bandwidth within 17%-28%. The results show our relative prediction model can obtain better prediction accuracy.

关键词： File systems Performance evaluation Predictive models Correlation Bandwidth Sun Synthetic aperture sonar

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Gaussian process based state estimation for a gyroscope-free IMU

Gaussian process based state estimation for a gyroscope-free...

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IEEE SENSORS

作者： Patrick Schopp Axel Rottmann Lasse Klingbeil Wolfram Burgard Yiannos Manoli Fritz Huettinger Chair of Microelectronics Department of Microsystems Engineering-IMTEK University of Freiburg Germany Department of Microsystems Engineering - IMTEK Fritz Huettinger Chair of Microelectronics Department of Computer Science - IIF University of Freiburg Germany HSG-IMIT - Institute of Micromachining and Information Technology Villingen-Schwenningen Germany

A gyroscope-free inertial measurement unit (GF IMU) utilizes only accelerometers to determine the relative movement of a body. We consider the problem of merging the individual accelerometer measurements using an Unscented Kalman filter (UKF) to estimate the body motion. Conventionally, this is realized by a parametric observation model, which gives the expected sensor measurements. In this paper, we replace this model by a Gaussian process (GP). GPs are a state-of-the art non-parametric Bayesian regression framework. Thereby, the measurements are determined based on a sampled set of training data. No physical principles of the system must be described. In addition, we apply sparse GPs using pseudo-inputs to reduce computation time, while the estimation accuracy remains nearly constant. As a result, the filter cycle time decreases by a factor of 1.92. We present accuracy measurements obtained on a 3D rotation table and compare the results to estimates generated with a parametric model.

关键词： Training Mathematical model Accelerometers Acceleration Angular velocity Three dimensional displays Parametric statistics

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On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits 10

On signalling over Through-Silicon Via (TSV) interconnects i...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Roshan Weerasekera Matt Grange Dinesh Pamunuwa Hannu Tenhunen Centre of Microsystems Engineering Faculty of Science & Technology Lancaster University Lancaster UK Department of Electronics Computer and Software Systems KTH School of Information and Communication Technologies Kista Sweden

ISBN: (纸本)9783981080162

This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.

关键词： Through-silicon vias Integrated circuit interconnections Three-dimensional integrated circuits Crosstalk Silicon Circuit simulation Measurement Delay effects Voltage Virtual manufacturing

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Characteristics of subband current ratio in double-gate MOSFET

Characteristics of subband current ratio in double-gate MOSF...

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2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

作者： Lou, Haijun Lin, Xinnan Zhang, Lining Zhang, Xukai Xu, Jiaojiao Wu, Wen Liu, Zhiwei Wang, Wenping Zhao, Wei Ma, Yong He, Frank Chan, Mansun Key Laboratory of Integrated Microsystems School of Computer and Information Engineering Peking University Shenzhen Graduate School Shenzhen 518055 China Peking University Shenzhen SOC Key Laboratory PKU HKUST Shenzhen Institute Hi-Tech. Industrial Park South Shenzhen 518057 China Department of ECE Hong Kong University of Science and Technology Kowloon Hong Kong

ISBN: (纸本)9781424499977

The subband current is evaluated by solving the non-equilibrium Green's function (NEGF) self-consistently with Poisson's equation for the double-gate MOSFETs with different channel lengths and thicknesses. The characteristics of subband current ratio and the details of subband number M are simulated, and the results show that the characteristics of current are determined by the first subband when TSi is smaller than 2.5nm, while the value of T Si is between 3.5nm and 5nm, the current of the second subband needs to be considered. The subband current ratios are highly related to the gate voltage, while less sensitive to the channel length. The suitable subband number M is also discussed for the devices with different sizes, which must be considered in balancing the model accuracy and the efficiency. © 2010 IEEE.

关键词： Poisson equation

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