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Mortality Dependence of Cu Dual Damascene Interconnects on Adjacent Segment

MRS Online Proceedings Library (OPL) 2011年第1期812卷 F7.2-F7.2页

作者： C.W. Chang C.L. Gan C.V. Thompson K.L. Pey W.K. Choi N. Hwang Advanced Materials for Micro- and Nano-Systems Singapore-MIT Alliance 4 Engineering Drive 3 Singapore 117576 School of Materials Engineering Nanyang Technological University Nanyang Avenue Singapore 639798 Department of Materials Science and Engineering Massachusetts Institute of Technology Cambridge Massachusetts 02139 School of Electrical & Electronics Engineering Nanyang Technological University Nanyang Avenue Singapore 639798 Department of Electrical and Computer Engineering National University of Singapore 4 Engineering Drive 3 Singapore 117576 Microsystems Modules & Components Laboratory Institute of Microelectronics Singapore 11 Science Park Road Singapore Science Park II Singapore 117685

Three terminal ‘dotted-I’ interconnect structures, with vias at both ends and an additional via in the middle, were tested under a variety of test conditions. Failures (mortalities) were observed even when segments were tested under conditions that would not have led to failure in two-terminal structures. Mortalities were found in right segments with jL values as low as 1250 A/cm, which is lower when compared to the immortality condition (jL)cr of 3700 A/cm reported for similar via-terminated structures. Moreover, we found that the mortality of a dotted-I segment is dependent on the direction and magnitude of the current in the adjacent segment. These results suggest that there is not a definite value of the jL product that defines true immortality in individual segments that are part of an interconnect tree. More importantly, the critical jL value for a single segment of Cu interconnects may be reduced or increased by an adjacent segment. Therefore independently determined (jL)cr values cannot be directly applied to interconnects with branched segments, but rather the magnitude as well as the direction of the current flow in the adjoining segments must be taken into consideration in evaluating the immortality of interconnect segments in an interconnect network.

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A unified drain current model for nanoscale double-gate and surrounding-gate MOSFETs incorporating velocity saturation

A unified drain current model for nanoscale double-gate and ...

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IEEE International Nanoelectronics Conference (INEC)

作者： Lining Zhang Xingye Zhou Yiwen Xu Lin Chen Wang Zhou Yingxue Li Frank He Mansun Chan Key Laboratory of Integrated Microsystems Peking University Shenzhen China TSRC School of Electronic Engineering and Computer Science Peking University Beijing China Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology Hong Kong China

A unified drain current model for undoped or lightly doped double-gate (DG) and surrounding-gate (SRG) MOSFETs incorporating velocity saturation effect are presented in this paper. The unified charge-based core model for undoped or lightly doped DG and SRG MOSFETs is presented first. Caughey-Thomas engineering mobility model with exponent factor n=2 is then integrated self-consistently into the unified drain current model derivation of the two device structure. Extensive two dimensional (2D) and three dimensional (3D) device simulations are performed to validate the proposed model. Symmetry property of the proposed unified current model is obtained with the exponent factor n=2 in Cauhey-Thomas Model.

关键词： MOSFETs Electron devices Solid modeling Geometry Semiconductor device modeling Nanoscale devices Integrated circuit modeling Testing Helium Electrostatics

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Correlation between gated-diode R-G current and performance degradation of SOI n-MOSFETs after F-N stress test

Correlation between gated-diode R-G current and performance ...

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作者： Bian, Wei Yan, Zhifeng He, Jin Ma, Chenyue Zhang, Chenfei Chan, Mansun Key Laboratory of Integrated Microsystems School of Computer and Information Engineering Peking University Shenzhen Graduate School Shenzhen 518055 China TSRC Institute of Microelectronics School of Electronic Engineering and Computer Science Beijing 100871 China Peking University Shenzhen SOC Key Laboratory PKU HKUST Shenzhen Institute W303 West Tower IER Bldg. Hi-Tech Industrial Park South Shenzhen 518057 China Department of Electrical and Computer Engineering Hong Kong University of Science and Technology Clear Water Bay Koloon Hong Kong

ISBN: (纸本)9781439834022

A correlation between the gated-diode R-G current and the performance degradation of SOI n-channel MOS transistor after F-N stress test has been demonstrated in this paper. Due to increase of interface traps after F-N stress test, the generation-recombination (R-G) current of the gated-diode in the SOI-MOSFET architecture increases while the performance characteristics of MOSFET transistor such as the saturation drain current and sub-threshold slope generate degradation. From a series of experimental measurements of the gated-diode and the SOI-MOSFET DC characteristics, a linear decrease of the drain saturation current and increase of the threshold voltage as well as the like-line rise of the sub-threshold swing and the corresponding degradation of the trans-conductance are also observed. These results provide theoretical and experimental evidences for us to use the gated-diode tool to monitor SOI-MOSFET degradation.

关键词： MOSFET devices

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A potential-based analytic model for monocrystalline silicon thin-film transistors on glass substrates

A potential-based analytic model for monocrystalline silicon...

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International Conference on Solid-State and Integrated Circuit technology

作者： Shaodi Wang Lining Zhang Jian Zhang Wenping Wang Wen Wu Xukai Zhang Zhiwei Liu Wei Bian Frank He Mansun Chan Shenzhen SOC Key Laboratory Peking University Shenzhen China The Key Laboratory of Integrated Microsystems School of Computer & Information EngineeringShenzhen Graduate School Peking University Shenzhen China Peking University Beijing Beijing CN Department of ECE Hong Kong University of Science and Technology Kowloon Hong Kong China

ISBN: (纸本)9781424457977

In this paper a potential based model for monocrystalline silicon thin film transistor (TFT) systems on glass (SOG) substrate from the accumulation to the strong-inversion region is developed. By solving the complete dimensional (1D) Poisson's equation, the potential distribution in the channel is obtained. The analytic drain current is expressed accurately base on the potential solution. Compared with TCAD simulations, the proposed current model shows less than 1.05% errors, with the doping concentrations ranging from 1.5 × 10 16 cm -3 to 1.5 × 10 18 cm -3 and different bias conditions. The proposed model is appropriate for precise and quick circuit simulation.

关键词： Mathematical model Semiconductor process modeling Numerical models Thin film transistors Integrated circuit modeling Doping Numerical simulation

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A surface potential-based non-charge-sheet core model for undoped surrounding-gate MOSFETs

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Journal of Semiconductors 2009年第2期30卷 30-33页

作者：何进张健张立宁马晨月陈文新 The Key Laboratory of Integrated Microsystems Peking University Shenzhen Graduate School TSRC and ULTRAS Team EECSPeking University Department of Electronics and Computer Engineering Hong Kong University of Science & Technology

A surface potential based non-charge-sheet core model for cylindrical undoped surrounding-gate （SRG） MOSFETs is presented. It is based on the exact surface potential solution of Poisson＇s equation and Pao-Sah＇s dual integral without the charge-sheet approximation, allowing the SRG-MOSFET characteristics to be adequately described by a single set of the analytic drain current equation in terms of the surface potential evaluated at the source and drain ends. It is valid for all operation regions and traces the transition from the linear to saturation and from the sub-threshold to strong inversion region without fitting-parameters, and verified by the 3-D numerical simulation.

关键词： non-classical MOS transistor surrounding-gate MOSFETs device physics surface potential model non-charge-sheet approximation

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Strained-$\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{Si}$ Band-to-Band Tunneling Transistors: Impact of Tunnel-Junction Germanium Composition and Doping Concentration on Switching Behavior

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IEEE Transactions on Electron Devices 2009年第10期56卷 2264-2269页

作者： Osama M. Nayfeh Judy L. Hoyt Dimitri A. Antoniadis Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

Strained pseudomorphic Si/Si 1-x Ge x /Si gate-controlled band-to-band tunneling (BTBT) devices have been analyzed with varying Ge composition up to 57% and p+ tunnel-junction (source) doping concentration in the 10 19 -10 20 cm -3 range. Measurements show the impact of these parameters on the transfer and output characteristics. Measurements are compared to simulations using a nonlocal BTBT model to analyze the mechanisms of device operation and to understand the impact of these parameters on the device switching behavior. The measured characteristics are consistent with simulation analysis that shows a reduction in energy barrier for tunneling (E geff ) and a reduction in tunneling distance with increasing Ge composition and source doping concentration. Increases in the pseudomorphic layer Ge content and doping concentration of the tunnel junction produce large improvements in the measured switching-behavior characteristics (I on , slope, turn-on voltages, and sharpness of turn-on as a function of V ds ). Simulations are also performed to project the potential performance of more optimized structures that may be suitable for extremely low power applications (V dd < 0.4 V).

关键词： Tunneling Semiconductor process modeling Doping Current measurement Silicon Logic gates Junctions

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Performance comparison of four-socket server architecture on HPC workload

Performance comparison of four-socket server architecture on...

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2009 International Conference on Computational science and Engineering, CSE '09

作者： Kasim, Henry March, Verdi See, Simon School of Mechanical and Aerospace Engineering Nanyang Technological University Singapore Department of Computer Science National University of Singapore Singapore Asia-Pacific Science and Technology Center Sun Microsystems Inc. United States

ISBN: (纸本)9780769538235

Recent server architectures embrace a common technology feature: on-chip parallelism via multi-core and CMT (Chip Multi Threading) technologies. However, they also significantly differ in a number of key aspects including clock speed, micro-architecture, cache hierarchy, and memory sub-system. Such differences may lead to difference levels of application performance. This paper presents a performance comparison of the recent four-socket server architecture on various high performance computing (HPC) workloads. Our analysis is based on two benchmark suites from Standard Performance Evaluation Corporation (SPEC): SPEC CPU2006 and SPEC OMP2001. Our analysis shows that no single architecture is the best for all types of workload. In addition, we found that the CPU clock speed, which is often used as the sole performance indicator, does not always reflect application performance.

关键词： Benchmarking

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Data mining analysis to validate performance tuning practices for HPL

Data mining analysis to validate performance tuning practice...

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2009 IEEE International Conference on Cluster Computing and Workshops, CLUSTER '09

作者： Tan, Tuan Zea Mong Goh, Rick Siow March, Verdi See, Simon Advanced Computing Institute of High Performance Computing Singapore Singapore Asia-Pacific Science and Technology Center Sun Microsystems Inc. Department of Computer Science National University of Singapore Singapore Department of Mechanical and Aerospace Engineering Nanyang Technological University Singapore Singapore

ISBN: (纸本)9781424450121

Applications performance is a criterion for system evaluation, and hence performance tuning for these applications is of great interest. One such benchmark application is High Performance Linpack (HPL). Although guidelines exist for HPL tuning, validating these guidelines on various systems is a challenging task as a large number of configurations need to be tested. In this work, we use data mining analysis to reduce the number of configurations to be tested in validating the HPL tuning guidelines on the Ranger System. We validate that NB, P and Q are the three most important parameters to tune HPL, and that PMAP does not have a significant impact on HPL performance. We also validate the practice of tuning HPL at small N using data mining analysis. We find that the value of N selected for tuning should not be significantly smaller than the largest N that can fit into the system memory. Our results indicate that data mining could be further applied to application performance tuning. © 2009 IEEE.

关键词： Data mining

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On-Wafer Seamless Integration of GaN and Si (100) Electronics

On-Wafer Seamless Integration of GaN and Si (100) Electronic...

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IEEE Symposium on Compound Semiconductor Integrated Circuit (CSICS)

作者： Jin Wook Chung Bin Lu Tomas Palacios Department of Electrical Engineering and Computer Science and Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA

The high thermal stability of nitride semiconductors allows for the on-wafer integration of (001)Si CMOS electronics and electronic devices based on these semiconductors. This paper describes the technology developed at MIT to seamlessly integrate GaN and Si transistors in very close proximity (<5 mum). This integration, the first of any III-V field effect transistor with (001) Si electronics, enables tremendous new possibilities to circuit and system designers. For example, we will study the use of hybrid GaN-Si circuits to improve the power distribution networks in Si microprocessors.

关键词： Gallium nitride Substrates CMOS technology HEMTs MODFETs Frequency Radiofrequency amplifiers Gallium arsenide MOSFETs Epitaxial growth

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An analytic model of the silicon-based nanowire Schottky Barrier MOSFET

An analytic model of the silicon-based nanowire Schottky Bar...

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作者： Zhou, Xingye Che, Yuchi Zhang, Lining He, Jin Chan, Mansun Key Laboratory of Integrated Microsystems Micro and Nano Electronic Device and Integrated Technology Center Shenzhen Graduate School of Peking University Shenzhen 518055 China Key Laboratory of Microelectronic Devices and Circuits of Ministry of Education School of Electronics Engineering and Computer Science Peking University 100871 China Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Clearwater Bay Kowloon Hong Kong

ISBN: (纸本)9781439817841

In this paper, an analytic model of the Silicon-based Nanowire Schottky-Barrier MOSFETs is developed based on the 2D solution of body potential together with the WKB tunneling theory. The proposed model predicts the electrical characteristics of the silicon-based nanowire Schottky barrier MOSFETs with different geometry and structure parameters and extensive comparisons with the 2-D numerical simulation show that the presented model is valid for all operation regions of such a device with a variety of geometry parameters and different work function configurations of the metal source (drain). Such a compact model may be useful for us to benchmark nanowire Schottky barrier MOSFET circuit performance and device structure optimization.

关键词： Nanowires

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