检索结果-内蒙古大学图书馆

International Electron Devices Meeting (IEDM)

作者： H.M. Nayfeh J.L. Hoyt D.A. Antoniadis IBM Semiconductor Research and Development Center NY USA Department of Electrical Engineering and Computer Science Microsystems Technology Laboratory Massachusetts Institute of Technology USA

The performance, calculated in terms of on-current I/sub on/ vs. off-current I/sub off/, of strained Si n-MOSFETs is compared to bulk (unstrained) Si devices with gate lengths down to 22 nm using hydrodynamic simulations with calibrated strained Si transport models. Strain results in I/sub on/ enhancement for given I/sub off/, but increased Coulomb scattering in strained Si super-halo n-MOSFETs with gate lengths approaching 25 nm and surface doping near 6/spl times/10/sup 18/ cm/sup -3/, results in reduction of I/sub on/ enhancement by approximately 10%. Simulations also indicate that the use of a gate electrode material with workfunction larger than n/sup +/ polysilicon is an attractive approach to achieve the desired off-current for strained devices scaled below 25 nm gate length, and for devices with increased strain in the channel (i.e. substrate Ge contents >20% Ge).

关键词： MOSFET circuits Acoustic scattering Threshold voltage Semiconductor process modeling Capacitive sensors Doping profiles Electric variables measurement Acoustic measurements Surface fitting Laboratories

来源：评论

学校读者我要写书评

暂无评论

Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression

Decompression hardware determination for test volume and tim...

引用

VLSI Test Symposium

作者： I. Bayraktaroglu A. Orailoglu Sun Microsystems Test Technology Group Sunnyvale CA USA Computer Science & Engineering Department University of California San Diego La Jolla CA USA

A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed. Test cube information is utilized for the determination of a near optimal decompression hardware. The proposed scheme attains simultaneously high compression levels and reduced pattern counts through a linear decompression hardware. Significant test volume and test application time reductions are delivered through the scheme we propose while a highly cost effective hardware implementation is retained.

关键词： Testing Hardware Compaction Costs Test pattern generators Sun computer science Moore's Law Sequential analysis Pins

来源：评论

学校读者我要写书评

暂无评论

Transport properties of polycrystalline Si/sub 0.8/Ge/sub 0.2/ thin films for micro power generators

Transport properties of polycrystalline Si/sub 0.8/Ge/sub 0....

引用

International Conference on Thermoelectrics (ICT)

作者： M. Takashiri T. Borca-Tasciuc O. Olubuyide A. Jacquot J. Hoyt G. Chen Mechanical Engineering Department Massachusetts Institute of Technology Cambridge MA USA Research Division Komatsu Limited Hiratsuka Kanagawa Japan Department of Mechanical Aerospace and Nuclear Engineering Rensselaer Polytechnic Institute Troy NY USA Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA LPM UMR CNRS-INPL-UHP 7556 Ecole des Mines Nancy France

The transport properties of polycrystalline Si/sub 0.8/Ge/sub 0.2/ thin films are studied for their potential applications in micro power generators. These thin films are deposited by low-pressure chemical deposition (LPCVD). The doping is carried out by boron and phosphorus ion implantation, followed by annealing in nitrogen ambient. The concentration of boron and phosphorus 4.3x10/sup 19/ cm/sup -3/, and 8.7x10/sup 19/ cm/sup -3/, respectively. The thermoelectric transport properties of these thin films are measured, including electrical conductivity, Seebeck coefficient, and thermal conductivity. The electrical conductivity is measured by a 4 point-probe method. The Seebeck coefficient is measured by applying a temperature gradient along the in-plane direction, and evaluating the resulting voltage. The thermal conductivity is measured by a 3/spl omega/ method in the cross-plane direction.

关键词： Thermal conductivity Conductivity measurement Boron Electric variables measurement Semiconductor thin films Power generation Sputtering Chemicals Doping Ion implantation

来源：评论

学校读者我要写书评

暂无评论

CoStore: a storage cluster architecture using network attached storage devices

CoStore: a storage cluster architecture using network attach...

引用

International Conference on Parallel and Distributed Systems (ICPADS)

作者： Yong Chen L.M. Ni Mingyao Yang Department of Computer Science and Engineering Michigan State University USA Department of Computer Science Hong Kong University of Science and Technology Hong Kong China Java Software Sun Microsystems Inc. USA

We propose a storage cluster architecture CoStore, which evenly distributes system responsibilities across all collaborating cluster members without a separate central file manager. The serverless CoStore architecture has the potential to provide scalable high-performance high-capacity storage services with strong reliability and availability, traditionally only achievable by high-end storage systems. A prototype CoStore system has been implemented using cost-effective COTS-based network attached storage devices on commodity operating systems. The performance of the CoStore prototype has been measured and compared with those of other commonly available distributed file systems. Preliminary test results show that a single node CoStore has a comparable performance to that of NFS and that CoStore outperforms CIFS on Windows 2000.

关键词： computer architecture Home appliances File systems Storage area networks Availability Disk drives computer science Collaborative software Prototypes Reliability engineering

来源：评论

学校读者我要写书评

暂无评论

Sub-10 cm/sup 3/ interferometric accelerometer with nano-g resolution

引用

Journal of Microelectromechanical Systems 2002年第3期11卷 182-187页

作者： N.C. Loh M.A. Schmidt S.R. Manalis Media Laboratory Massachusetts Institute of Technology Cambridge MA USA Zyomyx Inc. Hayward CA USA Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachsuetts lnstitute of Technology Cambridge MA USA Media Laboratory MIT Cambridge MA USA

A high-resolution accelerometer with a bulk-micromachined silicon proof mass and an interferometric position sensor was developed for measuring vibratory accelerations. The interferometer consists of interdigitated ringers that are alternately attached to the proof mass and support substrate. Illuminating the fingers with coherent light generates a series of diffracted beams. The intensity of a given beam depends on the out-of-plane separation between the proof mass fingers and support fingers. Proof masses with mechanical resonances ranging from 80 Hz to 1 kHz were fabricated with a two mask process involving two deep reactive ion etches, an oxide etch stop, and a polyimide protective layer. The structures were packaged with a laser diode and photodiode into 8.6-cm/sup 3/ acrylic housings. The 80-Hz resonant proof mass has a noise equivalent acceleration of 40 ng/rt Hz and a dynamic range of 85 dB at 40 Hz.

关键词： Fingers Optical interferometry Acceleration Resonance Etching Accelerometers Silicon Position measurement Vibration measurement Diffraction

来源：评论

学校读者我要写书评

暂无评论

Editorial

引用

IEEE Transactions on Semiconductor Manufacturing 2002年第1期15卷

作者： D.S. Boning Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Cambridge MA USA

来源：评论

学校读者我要写书评

暂无评论

A diaphragm-gate transistor for MEMS microphones

A diaphragm-gate transistor for MEMS microphones

引用

Annual Conference of Industrial Electronics Society

作者： M.T. Moskowitz A.M. Hodge R.W. Newcomb Electrical and Computer Engineering Johns Hopkins University Baltimore MD USA Electronic Science and Technology Division Naval Research Laboratory Inc. Washington D.C. DC USA Department of Electrical Engineering Microsystems Laboratory University of Maryland College Park MD USA

We present a process that can be manipulated to build pressure transducers very simply, using standard post fabrication procedure. This process is cost efficient, requiring but one extra step subsequent to standard MOSIS fabrication. Strategically placing hollowed insertions, and filling with hydrofluoric acid, allows for the etching of an underlying gate oxide. The resulting cavity turns the layer above it into a diaphragm that produces an output voltage in commensurate with air pressure impingent on the surface. We present an analog circuit used to handle the output signal, and discuss future possibilities for using this device as a microphone.

关键词： Micromechanical devices Microphones Etching Fabrication Capacitance Silicon Laboratories Educational institutions Transducers Costs

来源：评论

学校读者我要写书评

暂无评论

Variation issues in on-chip optical clock distribution

Variation issues in on-chip optical clock distribution

引用

IEEE International Workshop on Statistical Metrology

作者： Shiou Lin Sam A. Chandrakasan D. Boning Microsystems Technology Laboratories Electrical Engineering and Computer Science Department Massachusetts Institute of Technology Cambridge MA USA

ISBN: (纸本)0780366883

On-chip optical clock distribution is being investigated as a future means to increase clock speed and reduce clock power. While extremely small skew in the arrival of an on-chip optical signal can be achieved, the conversion of the optical signal to a local electrical clock may be subject to substantial variation. A baseline receiver circuit has been designed and fabricated. We find that sensitivity to device and operating condition variation reintroduces substantial clock skew. Future optical on-chip clock design approaches must take such variation sources into account.

关键词： Clocks Optical receivers Optical sensors Circuits Optical noise Optical waveguides Optical design Geometrical optics Detectors Optical amplifiers

来源：评论

学校读者我要写书评

暂无评论

Optical solder bumps: a modular approach to monolithic optoelectronic integration

Optical solder bumps: a modular approach to monolithic optoe...

引用

International Symposium Semiconductor Device Research (ISDRS)

作者： C.G. Fonstad Vitesse Professor of Electrical Engineering Department of Electrical Engineering and Computer Science and Microsystems Technology Laboratory Massachusetts Institute of Technology Cambridge MA USA

ISBN: (纸本)0780374320

The monolithic integration of compound semiconductor devices with silicon CMOS ICs is complicated by two major factors: the large thermal expansion coefficient mismatch between silicon and other semiconductors, and the large mismatch in wafer diameters between silicon and other semiconductors. Hence, most integration of compound semiconductors and silicon is done a chip at a time using long-established hybrid bump-bonding techniques. While these methods are able to begin to satisfy many immediate application needs, they do not enjoy the economic advantages of wafer-scale, batch processing found in true monolithic integration, nor to they offer the advantages of reduced parasitics, robustness of structure and density of integration that can be obtained from monolithic integration. This paper will present a philosophy for doing monolithic heterogeneous integration called the optical solder bump concept which strives to achieve all of the economic, structural and performance advantages of true monolithic integration and to do so in a modular fashion building upon commercial silicon integrated circuit processes.

关键词： Integrated optics Monolithic integrated circuits Silicon Gallium arsenide Dielectric substrates Optical devices Semiconductor devices Epitaxial growth Wafer bonding CMOS technology

来源：评论

学校读者我要写书评

暂无评论

Characterization of low temperature, wafer-level gold-gold thermocompression bonds

Characterization of low temperature, wafer-level gold-gold t...

引用

Materials science of Microelectromechanical Systems (MEMS) Devices II

作者： Tsau, Christine H. Schmidt, Martin A. Spearing, S. Mark Department of Materials Science and Engineering Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA United States Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA United States Department of Aeronautics and Astronautics Massachusetts Institute of Technology Cambridge MA United States

Low temperature, wafer-level bonding offers several advantages in MEMS packaging, such as device protection during aggressive processing/handling and the possibility of vacuum sealing. Although thermocompression bonding can be achieved with a variety of metals, gold is often preferred because of its acceptance in die bonding [1] and its resistance to oxidation. This study demonstrates that the simultaneous application of moderate pressure (0.5 MPa) and temperature (300°C) produces strong wafer-level bonds. A four-point bend-delamination technique was utilized to quantify bond toughness. Test specimens exhibited constant load versus displacement behavior during steady state crack propagation. Two distinct fracture modes were observed: cohesive failure within the Au and adhesive failure at the Ti-Si interface. The strain energy release rate for Au-Au fracture was found to be higher than that associated with Ti-Si fracture, consistent with the greater plastic deformation that occurs in the metal during fracture.

关键词： Gold

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：