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Characterization of Low Temperature, Wafer-Level Gold-Gold Thermocompression Bonds

MRS Online Proceedings Library 2000年第1期605卷 171-176页

作者： Tsau, Christine H. Schmidtt, Martin A. Spearing, S. Mark Massachusetts Institute of Technology Cambridge USA Department of Materials Science and Engineering Microsystems Technology Laboratories USA partment of Electrical Engineering and Computer Science Microsystems Technology Laboratories USA Department of Aeronautics and Astronautics USA

Low temperature, wafer-level bonding offers several advantages in MEMS packaging, such as device protection during aggressive processing/handling and the possibility of vacuum sealing. Although thermocompression bonding can be achieved with a variety of metals, gold is often preferred because of its acceptance in die bonding [1] and its resistance to oxidation. This study demonstrates that the simultaneous application of moderate pressure (0.5 MPa) and temperature (300°C) produces strong wafer-level bonds. A four-point benddelamination technique was utilized to quantify bond toughness. Test specimens exhibited constant load versus displacement behavior during steady state crack propagation. Two distinct fracture modes were observed: cohesive failure within the Au and adhesive failure at the Ti-Si interface. The strain energy release rate for Au-Au fracture was found to be higher than that associated with Ti-Si fracture, consistent with the greater plastic deformation that occurs in the metal during fracture.

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Low temperature solid-source molecular-beam epitaxy growth of Al-free quantum well laser diodes using a GaP-decomposition source

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Journal of Vacuum science and technology B: Microelectronics and Nanometer Structures 1999年第3期17卷 1281-1284页

作者： Postigo, P.A. Lullo, G. Choy, K.H. Fonstad, C.G. Department of Electrical Engineering and Computer Science Microsystems Technology Laboratory Massachusetts Institute of Technology Cambridge MA 02139 United States

Low threshold aluminum-free, InGaP/GaAs/InGaAs quantum well laser diodes have been grown at low temperature on GaAs using a GaP sublimation source for phosphorous and an atomic hydrogen cracker source for substrate surface preparation. The growth cycle was conducted entirely below 470°C so that it is compatible with growth on GaAs very large scale integrated circuits, as in the epitaxy-on-electronics monolithic optoelectronic integration processes. The room temperature pulsed threshold current density of broad-area stripe contact laser diodes was consistently on the order of 0.38 kA/cm². InGaP grown with the GaP cell is found by secondary ion mass spectroscopy to contain significant amounts of oxygen, particularly in Be- and Si-doped layers. © 1999 American Vacuum Society.

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An undergraduate microfabrication project laboratory case study: the micromechanical contactor array

An undergraduate microfabrication project laboratory case st...

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University/Government/Industry Microelectronics Symposium

作者： Chi Hoang M.A. Schmidt Department of Electrical Engineering and Computer Science MicroSystems Technology Laboratories Cambridge MA USA

Summary form only given. For approximately ten years, MIT has supported an undergraduate project laboratory which teaches microfabrication process design. The project laboratory attempts to engage the students in projects which have a end goal of fabrication of a specific novel device, often with an end user that is supporting the laboratory portion of the course. In this paper, we will present the most recent results of teaching this course in the Spring '98 semester. The project this semester was to fabricate an array of micromechanical contactors which could be used in the high-speed testing of integrated circuits. We will describe the execution of the course in detail. A detailed description of the final device design and fabrication will be given with the measured results. We will summarize the lessons learned, particularly in relation to organizing a team of students on one project, and the nuances of working with an industrial sponsor in a course environment.

关键词： Laboratories Fabrication Circuit testing Process design Education Springs Micromechanical devices Contactors Integrated circuit testing High speed integrated circuits

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An improved NMOS AC hot-carrier lifetime prediction algorithm based on the dominant degradation asymptote

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IEEE TRANSACTIONS ON ELECTRON DEVICES 1997年第4期44卷 651-658页

作者： Kim, SWA Menberu, B Le, HXP Jiang, WJ Chung, JE Department of Electrical Engineering and Computer Science Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA

This study presents a new algorithm for improved prediction of ac hot-carrier lifetime, It is based on identifying and projecting the dominant degradation asymptote, The algorithm accounts for the stress-bias dependence of the hot-carrier degradation rate and the nonlinearity of the degradation time-dependence, Detailed model parameter extraction and lifetime prediction procedures are explained, and applications of the new algorithm demonstrated, Significant differences in the predicted ac-lifetimes are found between the existing and the new algorithms over a wide range of CMOS inverter design parameters, such as the input ramp rate and the load capacitance.

关键词： MOS devices Hot carriers Prediction algorithms Degradation Semiconductor device modeling Predictive models Parameter extraction Inverters Algorithm design and analysis Capacitance

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Analysis and decomposition of spatial variation in integrated circuit processes and devices

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 1997年第1期10卷 24-41页

作者： Stine, BE Boning, DS Chung, JE Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

Variation is a key concern in semiconductor manufacturing and is manifest in several forms, Spatial variation across each wafer results from equipment or process limitations, and variation within each die may be exacerbated further by complex pattern dependencies, Spatial variation information is important not only for process optimization and control, but also for design of circuits that are robust to such variation, Systematic and random components of the variation must be identified, and models relating the spatial variation to specific process and pattern causes are needed, In this work, extraction and modeling methods are described for wafer-level, die-level, and wafer-die interaction contributions to spatial variation. Wafer-level estimation methods include filtering, spline, and regression based approaches, Die-level (or intra-die) variation can be extracted using spatial Fourier transform methods;important issues include spectral interpolation and sampling requirements, Finally, the interaction between wafer- and die-level effects is important to fully capture and separate systematic versus random variation;spline- and frequency-based methods are proposed for this modeling, Together, these provide an effective collection of methods to identify and model spatial variation for future use in process control to reduce systematic variation, and in process/device design to produce more robust circuits.

关键词： Semiconductor device modeling Process control Circuits Robust control Spline Semiconductor device manufacture Design optimization Data mining Filtering Fourier transforms

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A flexible, distributed architecture for semiconductor process control and experimentation

A flexible, distributed architecture for semiconductor proce...

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Conference on Open Architecture Control Systems and Standards

作者： Gower, A Boning, D McIlrath, M Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA 02139 United States

ISBN: (纸本)0819423149

Semiconductor fabrication requires an increasingly expensive and integrated set of tightly controlled processes, driving the need for a fabrication facility with fully computerized, networked processing equipment. We describe an integrated, open system architecture enabling distributed experimentation and process control for plasma etching. The system was developed at MIT's microsystems technology Laboratories and employs in-situ CCD interferometry based analysis in the sensor-feedback control of an Applied Materials Precision 5000 Plasma Etcher (AME5000). Our system supports accelerated, advanced research involving feedback control algorithms, and includes a distributed interface that utilizes the internet to make these fabrication capabilities available to remote users. The system architecture is both distributed and modular: specific implementation of any one task does not restrict the implementation of another. The low level architectural components include a host controller that communicates with the AME5000 equipment via SECS-II, and a host controller for the acquisition and analysis of the CCD sensor images. A Cell Controller (CC) manages communications between these equipment and sensor controllers. The CC is also responsible for process control decisions;algorithmic controllers may be integrated locally or via remote communications. Finally, a System Server manages connections from internet/intranet (web) based clients and uses a direct link with the CC to access the system. Each component communicates via a predefined set of TCP/IP socket based messages. This flexible architecture makes integration easier and more robust, and enables separate software components to run on the same or different computers independent of hardware or software platform.

关键词： distributed architecture in-situ data acquisition semiconductor process control distributed interface

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Architecture for distributed design and fabrication

Architecture for distributed design and fabrication

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Plug and Play Software for Agile Manufacturing

作者： McIlrath, Michael B. Boning, Duane S. Troxel, Donald E. Massachusetts Institute of Technology Microsystems Technology Laboratories Department of Electrical Engineering and Computer Science Cambridge MA 02139 United States

We describe a flexible, distributed system architecture capable of supporting collaborative design and fabrication of semi-conductor devices and integrated circuits. Such capabilities are of particular importance in the development of new technologies, where both equipment and expertise are limited. Distributed fabrication enables direct, remote, physical experimentation in the development of leading edge technology, where the necessary manufacturing resources are new, expensive, and scarce. Computational resources, software, processing equipment, and people may all be widely distributed;their effective integration is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages is essential in order to achieve the realization of new technologies for specific product requirements. Our architecture leverages current vendor and consortia developments to define software interfaces and infrastructure based on existing and merging networking, CIM, and CAD standards. Process engineers and product designers access processing and simulation results through a common interface and collaborate across the distributed manufacturing environment. ©2005 Copyright SPIE - The International Society for Optical Engineering.

关键词： Fabrication

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Epitaxy-on-electronics enhancement of GaAs IC performance with monolithic optical and quantum-effect devices

Epitaxy-on-electronics enhancement of GaAs IC performance wi...

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Advanced Workshop on Frontiers in Electronics, WOFE

作者： C.G. Fonstad J.F. Ahadian S.G. Patterson P.T. Vaidyanathan Y. Royter G. Petrich L.A. Kolodziejski S. Prasad National Center for Integrated Photonics Technology (NCIPT) Research Laboratory of Electronics (RLE) Microsystems Technology Laboratory and Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

An integration technique, epitaxy-on-electronics (EoE), is described wherein optoelectronic and quantum effect device heterostructures are grown on fully processed GaAs integrated circuit chips and subsequently processed into devices monolithically integrated with the pre-existing circuitry. Using this technique, one can realize the increased performance and functionality promised by adding advanced heterostructure quantum effect and optoelectronic devices to conventional integrated electronic circuitry, without developing a complete new VLSI technology. The details of the EoE technology are explained, and examples of optoelectronic integrated circuits incorporating LEDs, detectors, and MESFET electronics are presented. The OPTOCHIP Project, a prototype EoE research OEIC foundry, and work on EoE integration of resonant tunneling diodes to form one-transistor GaAs static random access memory cells, are also described.

关键词： Gallium arsenide Optoelectronic devices Integrated circuit technology MESFET integrated circuits Monolithic integrated circuits Very large scale integration Light emitting diodes Detectors Prototypes Foundries

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Multi-path routing combined with resource reservation

Multi-path routing combined with resource reservation

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IEEE Annual Joint Conference: INFOCOM, IEEE computer and Communications Societies

作者： I. Cidon R. Rom Y. Shavitt Department of Electrical Engineering Technion-Israel Institute of Technology Haifa Israel Sun Microsystems Inc. Mountain View CA USA Department of Computer Science Johns Hopkins University Baltimore MD USA

In high-speed networks it is desirable to interleave routing and resource (such as bandwidth) reservation. The PNNI standard for private ATM networks is an example of an algorithm that does this using a sequential crank-back mechanism. We suggest the implementation of resource reservation along several routes in parallel. We present an analytical model that demonstrates that when there are several routes to the destination it pays to attempt reservation along more than a single route. Following this analytic observation, we present a family of algorithms that route and reserve resources along parallel subroutes. The algorithms of the family represent different trade-offs between the speed and the quality of the established route. The presented algorithms are simulated against several legacy algorithms, including the PNNI crank-back, and exhibit higher network utilization and faster connection set-up time.

关键词： Routing Sun Electronic mail High-speed networks Bandwidth B-ISDN Availability Read only memory computer science Analytical models

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Design and fabrication of micromachined passive microwave filtering elements in CMOS technology

Design and fabrication of micromachined passive microwave fi...

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International Conference on Solid State Sensors and Actuators (TRANSDUCERS)

作者： V. Milanovic M. Gaitan E.D. Bowen N.H. Tea M.E. Zaghloul Department of Electrical Engineeridng and Computer Science George Washington University Washington D.C. DC USA Semiconductor Electronics Division National Institute for Standards and Technology Gaithersburg MD USA RF Microsystems Inc. San Diego CA USA

This paper describes a novel implementation of micromachined microwave resonators and filters, coupled with low-loss transmission lines, fabricated in standard CMOS technology. Selective etching of the Si substrate beneath the microwave elements results in significantly lowered transmission loss, improved quality factor and operating frequency range. This allows operation at gigahertz frequencies. Resonators with Q-factors of 20 and resonant frequencies of 2 GHz and 21 GHz are reported which are significant results for standard CMOS technology. A low-pass filter is also reported with a 2.5 GHz cutoff frequency. The resonant and cutoff frequencies are in general adjustable within the 1 to 40 GHz band. These devices are useful for integration with microwave power sensors, and have application in wireless communication systems where low-loss operation above 1 GHz is essential.

关键词： Fabrication Microwave filters Passive filters CMOS technology Resonator filters Q factor Cutoff frequency Filtering Couplings Power transmission lines

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