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6th International Workshop on FPGAs for Software Programmers, FSP 2019, co-located with International Conference on Field Programmable Logic and Applications, FPL 2019

作者： Kenter, Tobias Paderborn Center for Parallel Computing Department of Computer Science Paderborn University Warburger Str. 100 Paderborn33098 Germany

ISBN: (纸本)9783800750467

An increasing fraction of new results in the reconfigurable computing domain are obtained with the help of high level synthesis tools. Among the more popular tools are the OpenCL based Xilinx SDAccel and Intel FPGA SDK for OpenCL. Since they are building upon the same programming model and source language, one would hope for portability between different OpenCL based FPGA designs. However, the vast majority of published research is only optimized for one vendor tool and FPGA family. In this manuscript, we want to broaden that scope and provide practical guidance for both tool chains. We outline the common underlying design philosophy and goals of high level synthesis for FPGAs on an abstract level, before proceeding to an example-driven discussion of tool features and concepts. We present design patterns that work well for both tools and thus can promote portability of OpenCL based FPGA designs. We outline how tool differences that can be overcome for portability, or used for further optimized tool-specific designs. © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： Field programmable gate arrays (FPGA)

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HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory 32

HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchi...

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32nd IEEE Annual International Symposium on Field-Programmable Custom computing Machines, FCCM 2024

作者： Tareen, Abdul Rehman Meyer, Marius Plessl, Christian Kenter, Tobias Paderborn University Paderborn Center for Parallel Computing Department of Computer Science Warburger Str. 100 Paderborn33098 Germany

ISBN: (纸本)9798350372434

The multiplication of a sparse matrix with a dense vector is a vital operation in linear algebra, with applications in numerous contexts. After earlier research on FPGA acceleration of this operation had shown the potential to achieve a high bandwidth efficiency, this workload has received renewed attention with the introduction of high bandwidth memory on FPGA platforms. However, previous designs fell short of scaling to the full bandwidth potential of current FPGA platforms with high bandwidth memory. In this work, we present HiHiSpMV with a novel design approach around hierarchical accumulation, which allows us to overcome several limitations of the related work. Our design is completely implemented with high-level synthesis and compiled with Vitis, and instantiates 16 independent compute units, each processing up to 16 matrix elements per clock cycle. The reduction of these elements is performed without any latency or resource overhead and the subsequent accumulation uses the well-established shift-register design pattern. Due to the independent nature of compute units, our design can connect to all of the 32 high bandwidth memory pseudo-channels in 512-bit interface mode on an Alveo U280 FPGA board. In our tests, we reach up to 86% of the theoretical available bandwidth of this FPGA platform, enabling a computational throughput of up to 98 GFLOPS. This is about 1.5 × faster than the peak throughput of the best related work in that regard, Serpens. On average, the throughput of HiHiSpMV is even 2.7× higher than Serpens. © 2024 IEEE.

关键词： Shift registers

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PadFEM: A portable parallel FEM-tool

PadFEM: A portable parallel FEM-tool

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International Conference and Exhibition on High-Performance computing and Networking, HPCN EUROPE 1996

作者： Diekmann, Ralf Dralle, Uwe Neugebauer, Friedhelm Römke, Thomas Department of Computer Science University of Paderborn Paderborn33095 Germany Paderborn Center for Parallel Computing PC 2 University of Paderborn Paderborn33095 Germany

ISBN: (纸本)9783540611424

We present a modular toolbox for parallel finite element simulations on distributed memory systems. The library named PadFEM includes a graphical editor for specifying domains with boundary conditions, automatic mesh generation, automatic mesh partitioning and mapping onto the processors of a MIMD-system. The parallel FEM-simulation uses the preconditioned conjugate gradient method. The parallelization is based on PVM which guarantees portable parallel code. The current implementation is able to solve the two-dimensional Poisson equation in arbitrary domains with mixed Dirichlet- and Neumann-type boundary conditions using triangular meshes. The modular structure based on the idea of programming frames allows an easy extension to other problems. © Springer-Verlag Berlin Heidelberg 1996.

关键词： Boundary conditions

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Heuristic solutions for a mapping problem in a TV-Anytime server network

Heuristic solutions for a mapping problem in a TV-Anytime se...

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15 Workshops Held in Conjunction with the IEEE International parallel and Distributed Processing Symposium, IPDPS 2000

作者： Zhou, Xiaobo Lüling, Reinhard Xie, Li Paderborn Center for Parallel Computing University of Paderborn Fürstenallee 11 D-33102 Paderborn Germany Department of Computer Science Nanjing University China

ISBN: (纸本)354067442X

This paper presents a novel broadband multimedia service called TV-Anytime. The basic idea of this service is to store broadcast media assets onto media server systems and allow clients to access these streams at any time. We propose a hierarchical structure of a distributed server network to support a high quality TV-anytime service. A key issue, how to map the media assets onto such a hierarchical server network is addressed and formalized as a combinatorial optimization problem. In order to solve this optimization problem, a set of heuristic solutions by use of a parallel simulated annealing library is proposed and verified by a set of benchmark instances. Finally, the TV Cache is presented as a prototype of a scalable TV-Anytime system. © 2000 Springer-Verlag Berlin Heidelberg.

关键词： Simulated annealing

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parallel macro pipelining on the intel SCC many-core computer

Parallel macro pipelining on the intel SCC many-core compute...

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2013 IEEE 37th Annual computer Software and Applications Conference, COMPSAC 2013

作者： Suss, Tim Schoenrock, Andrew Meisner, Sebastian Plessl, Christian Johannes Gutenberg-University Mainz Zentrum fur Datenverarbeitung Mainz Germany Carleton University School of Computer Science Ottawa Canada University of Paderborn Paderborn Center for Parallel Computing Paderborn Germany

ISBN: (纸本)9780769549798

In this paper we present how Intel's Single-Chip-Cloud processor behaves for parallel macro pipeline applications. Subsets of the SCC's available cores can be arranged as a pipeline where each core processes one stage of the overall workload. Each of the independent cores processes a small part of a larger task and feeds the following core with new data after it finishes its work. Our case-study is a parallel rendering system which renders successive images and applies different filters on them. On normal graphics adapters this is usually done in multiple cycles, we do this in a single pipeline pass. We show that we can achieve a significant speedup by using multiple parallel pipelines on the SCC. We show that we can further improve performance by using SCC's controlling PC in conjunction with the SCC. We also identify aspects of the SCC that hinder the overall performance, mainly the lack of local memory banks for each core on the SCC. The results presented in this paper are not limited to only image processing, but users could expect similar experiences where macro pipelining is used in other applications on the SCC. © 2013 IEEE.

关键词： Pipelines

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SkewCCC+: A heterogeneous distributed hash table

SkewCCC+: A heterogeneous distributed hash table

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14th International Conference on Principles of Distributed Systems, OPODIS 2010

作者： Bienkowski, Marcin Brinkmann, André Klonowski, Marek Korzeniowski, Miroslaw Institute of Computer Science University of Wroclaw Poland Paderborn Center for Parallel Computing PC2 University of Paderborn Germany Inst. of Mathematics and Computer Science Wroclaw Univ. of Technology Poland

ISBN: (纸本)3642176526

Distributed Hash Tables (DHTs) enable fully distributed Peer-to-Peer network construction and maintenance with name-driven routing. There exist very few DHT approaches that consider heterogeneity of nodes inside the construction process or properly serve data of different load. To our best knowledge, there is no construction which smoothly addresses both these issues. We propose a Peer-to-Peer construction that explicitly uses heterogeneity to simplify the routing and maintenance process even in the presence of an adaptive adversary. Using a hypercube and cube connected cycles networks as a backbone, we show how to cope with two types of heterogeneity: one for nodes and one for data. © 2010 Springer-Verlag.

关键词： Peer to peer networks

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The HighPerMeshes framework for numerical algorithms on unstructured grids

The HighPerMeshes framework for numerical algorithms on unst...

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作者： Alhaddad, Samer Förstner, Jens Groth, Stefan Grünewald, Daniel Grynko, Yevgen Hannig, Frank Kenter, Tobias Pfreundt, Franz-Josef Plessl, Christian Schotte, Merlind Steinke, Thomas Teich, Jürgen Weiser, Martin Wende, Florian Paderborn Center for Parallel Computing and Department of Computer Science and Department of Electrical Engineering Paderborn University Paderborn Germany Erlangen Germany Fraunhofer Institut für Techno- und Wirtschaftsmathematik Kaiserslautern Germany Zuse Institute Berlin Germany

Solving partial differential equations (PDEs) on unstructured grids is a cornerstone of engineering and scientific computing. Heterogeneous parallel platforms, including CPUs, GPUs, and FPGAs, enable energy-efficient and computationally demanding simulations. In this article, we introduce the HighPerMeshes C++-embedded domain-specific language (DSL) that bridges the abstraction gap between the mathematical formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different programming models on the other hand. Thus, the HighPerMeshes DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HighPerMeshes DSL, and demonstrate its usage with three examples. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. A code generator and a matching back end allow the acceleration of HighPerMeshes code with GPUs. Finally, the achievable performance and scalability are demonstrated for different example problems. © 2021 The Authors. Concurrency and Computation: Practice and Experience published by John Wiley & Sons Ltd.

关键词： Problem oriented languages

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Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: From Describing Algorithms to Describing Architectures 24

Optimisation and Evaluation of Breadth First Search with one...

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12th International Workshop on OpenCL and SYCL, IWOCL 2024

作者： Olgu, Kaan Kenter, Tobias Nunez-Yanez, Jose McIntosh-Smith, Simon School of Electrical & Electronics Engineering University of Bristol United Kingdom Paderborn Center for Parallel Computing Department of Computer Science Paderborn University Germany Dept. Electrical Engineering Linkoping University Sweden

ISBN: (纸本)9798400717901

FPGAs are often used in scientific fields to process graph algorithms due to their energy efficiency, reconfigurability, and fine-grained parallelism. However, these algorithms face challenges in memory access patterns, scalability, and programmability. The SYCL2020 implementation in the Intel oneAPI toolchain supports FPGA targets alongside SYCL2020 features like modern C++ with a single-source offloading to improve programmability. This study analysed the Breadth-First Search algorithm on Stratix 10 FPGA with the Intel oneAPI toolchain. The implementation was done in two phases. At first, we applied the typical optimisations proposed in the official guidelines alongside an automatic cache to achieve proper pipelining and improve random memory accesses performance. However, limitations occurred with fine-grained parallelism, and it was competitive only to some related work that utilised hardware-description languages or established high-level synthesis tools. For the second phase, we added bit-level representations of data in memory, banking in on-chip memory, and fine-grained control over parallel data streams. The second implementation was generally superior or on par with all compared designs, outperforming other works in 10 out of 15 tested datasets, including various synthetic RMAT and real-world datasets, with a peak performance of 1021 MTEPS. © 2024 Owner/Author.

关键词： Field programmable gate arrays (FPGA)

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Demo abstract: Operating a sensor network at 3500 m above sea level

Demo abstract: Operating a sensor network at 3500 m above se...

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2009 International Conference on Information Processing in Sensor Networks, IPSN 2009

作者： Beutel, Jan Gruber, Stephan Hasler, Andreas Lim, Roman Meier, Andreas Plessl, Christian Talzi, Igor Thiele, Lothar Tschudin, Christian Woehrle, Matthias Yuecel, Mustafa Computer Engineering and Networks Lab. ETH Zurich Zurich Switzerland Physical Geography Division Department of Geography University of Zurich Switzerland Paderborn Center for Parallel Computing University of Paderborn Germany Computer Science Department University of Basel Switzerland

ISBN: (纸本)9781424451081

Sensor networks deployed in remote locations require easy to use but also extremely expressive tools for reliable operation. The PermaSense project has developed a platform based on a number of proven COTS components and integrated with the GSN based data backend. All tools are accessible from a single location in a web browser. This demo will present the monitoring and control tools in live operation with deployments on real field sites in the Swiss Alps.

关键词： Sensor networks

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High level synthesis implementation of a three-dimensional systolic array architecture for matrix multiplications on intel stratix 10 FPGAs

arXiv

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arXiv 2021年

作者： Gorlani, Paolo Plessl, Christian Paderborn Center for Parallel Computing Department of Computer Science Paderborn University Paderborn Germany

In this paper, we consider the HLS implementation of a three-dimensional systolic array architecture for matrix multiplication that targets specific characteristics of Intel Stratix 10 FPGAs in order to produce designs that achieve a high floating-point throughput using most of the DSPs at high frequencies in a way that avoids the congestion of the routing fabric. The investigated three-dimensional systolic array architecture is able to produce hardware designs that use 99% of the available DSPs with maximum frequencies that let us achieve performance above 3 TFLOPS. Copyright © 2021, The Authors. All rights reserved.

关键词： Matrix algebra

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