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International Conference on Field Programmable Logic and Applications

作者： Philip Stachura Guanyu Li Xin Wu Christian Plessl Zhenman Fang Simon Fraser University Burnaby BC Canada Paderborn Center for Parallel Computing Department of Computer Science Paderborn University Warburger Str. 100 Paderborn Germany

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

The computation of electron repulsion integrals (ERIs) is a key component for quantum chemical methods. The intensive computation and bandwidth demand for ERI evaluation presents a significant challenge for quantum-mechanics-based atomistic simulations with hybrid density functional theory: due to the tens of trillions of ERI computations in each time step, practical applications are usually limited to thousands of atoms. In this work, we propose SERI, a high-throughput streaming accelerator for ERI computation on HBM-based FPGAs. In contrast to prior buffer-based designs, SERI proposes a novel streaming architecture to address the on-chip buffer limitation and the floorplanning challenge, and leverages the high-bandwidth memory to overcome the bandwidth bottleneck in prior designs. Moreover, to meet the varying computation, bandwidth, and floorplanning requirements between the 55 canonical quartet classes in ERI calculation, we design an automation tool, together with an accurate performance model, to automatically customize the architecture and floorplanning strategy for each canonical quartet class to maximize their throughput. Our performance evaluation on the AMD/Xilinx Alveo U280 FPGA board shows that, SERI achieves an average speedup of 9.80 x over the previous best-performing FPGA design, a 3.21x speedup over a 64-core AMD EPYC 7713 CPU, and a 15.64x speedup over an Nvidia A40 GPU. It reaches a peak throughput of 23.8 GERIS ($10^{9}$ ERIs per second) on one Alveo U280 FPGA. SERI will be released soon at https://***/SFU-HiAccel/SERI.

关键词： Performance evaluation Computational modeling Quantum chemistry Quantum mechanics Bandwidth computer architecture Throughput System-on-chip Field programmable gate arrays Electrons

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computing and Compressing Electron Repulsion Integrals on FPGAs

Computing and Compressing Electron Repulsion Integrals on FP...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Xin Wu Tobias Kenter Robert Schade Thomas D. Kühne Christian Plessl Paderborn Center for Parallel Computing Paderborn University Paderborn Germany Department of Computer Science Paderborn University Paderborn Germany Department of Chemistry Paderborn University Paderborn Germany

The computation of electron repulsion integrals (ERIs) over Gaussian-type orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic simulations. In practical simulations, several trillions of ERIs may have to be computed for every time step. In this work, we investigate FPGAs as accelerators for the ERI computation. We use template parameters, here within the Intel oneAPI tool flow, to create customized designs for 256 different ERI quartet classes, based on their orbitals. To maximize data reuse, all intermediates are buffered in FPGA on-chip memory with customized layouts. The pre-calculation of intermediates also helps to overcome data dependencies caused by multi-dimensional recurrence relations. The involved loop structures are partially or even fully unrolled for high throughput of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary bitwidth integers is integrated in the FPGA kernels. To our best knowledge, this is the first work on ERI computation on FPGAs that supports more than just the single most basic quartet class. Also, the integration of ERI computation and compression is a novelty that is not even covered by CPU or GPU libraries so far. Our evaluation shows that using 16-bit integer for the ERI compression, the fastest FPGA kernels exceed the performance of 10 GERIS ( $10\times 10^{9}$ ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors around 10 −7 - 10 −5 Hartree. The measured throughput can be accurately explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform similar computations using the widely used libint reference on a two-socket server with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x.

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The HighPerMeshes framework for numerical algorithms on unstructured grids

The HighPerMeshes framework for numerical algorithms on unst...

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作者： Alhaddad, Samer Förstner, Jens Groth, Stefan Grünewald, Daniel Grynko, Yevgen Hannig, Frank Kenter, Tobias Pfreundt, Franz-Josef Plessl, Christian Schotte, Merlind Steinke, Thomas Teich, Jürgen Weiser, Martin Wende, Florian Paderborn Center for Parallel Computing and Department of Computer Science and Department of Electrical Engineering Paderborn University Paderborn Germany Erlangen Germany Fraunhofer Institut für Techno- und Wirtschaftsmathematik Kaiserslautern Germany Zuse Institute Berlin Germany

Solving partial differential equations (PDEs) on unstructured grids is a cornerstone of engineering and scientific computing. Heterogeneous parallel platforms, including CPUs, GPUs, and FPGAs, enable energy-efficient and computationally demanding simulations. In this article, we introduce the HighPerMeshes C++-embedded domain-specific language (DSL) that bridges the abstraction gap between the mathematical formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different programming models on the other hand. Thus, the HighPerMeshes DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HighPerMeshes DSL, and demonstrate its usage with three examples. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. A code generator and a matching back end allow the acceleration of HighPerMeshes code with GPUs. Finally, the achievable performance and scalability are demonstrated for different example problems. © 2021 The Authors. Concurrency and Computation: Practice and Experience published by John Wiley & Sons Ltd.

关键词： Problem oriented languages

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EFFICIENT SPECTRAL METHODS FOR EIGENVALUE PROBLEMS OF THE INTEGRAL FRACTIONAL LAPLACIAN ONABALLOFANYDIMENSION

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Journal of Computational Mathematics 2024年第4期42卷 1032-1062页

作者： Suna Ma Huiyuan Li Zhimin Zhang Hu Chen Lizhen Chen College of Science Nanjing University of Posts and TelecommunicationsNanjingChina State Key Laboratory of Computer Science/Laboratory of Parallel Computing Institute of SoftwareChinese Academy of SciencesBeijingChina Department of Mathematics Wayne State UniversityDetroitUSA School of Mathematical Sciences Ocean University of ChinaQingdaoChina Beijing Computational Science Research Center BeijingChina

An efficient spectral-Galerkin method for eigenvalue problems of the integral fractional Laplacian on a unit ball of any dimension is proposed in this *** symmetric positive definite linear system is retained explicitly which plays an important role in the numerical *** a sharp estimate on the algebraic system's condition number is established which behaves as N4s with respect to the polynomial degree N,where 2s is the fractional derivative *** regularity estimate of solutions to source problems of the fractional Laplacian in arbitrary dimensions is firstly investigated in weighted Sobolev *** the regularity of eigenfunctions of the fractional Laplacian eigenvalue problem is readily ***,rigorous error estimates of the eigenvalues and eigenvectors are *** experiments are presented to demonstrate the accuracy and efficiency and to validate the theoretical results.

关键词： Integral fractional Laplacian Spectral method Eigenvalue problem Regularity analysis Error estimate

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Optimizing Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL

arXiv

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arXiv 2024年

作者： Meyer, Marius Kenter, Tobias Petrica, Lucian O’Brien, Kenneth Blott, Michaela Plessl, Christian Paderborn University Department of Computer Science Warburger Str. 100 Paderborn Germany Paderborn Center for Parallel Computing Mersinweg 5 Paderborn Germany AMD Research 2020 Bianconi Ave Dublin Ireland

Most FPGA boards in the HPC domain are well-suited for parallel scaling because of the direct integration of versatile and high-throughput network ports. However, the utilization of their network capabilities is often challenging and error-prone because the whole network stack and communication patterns have to be implemented and managed on the FPGAs. Also, this approach conceptually involves a trade-off between the performance potential of improved communication and the impact of resource consumption for communication infrastructure, since the utilized resources on the FPGAs could otherwise be used for computations. In this work, we investigate this trade-off, firstly, by using synthetic benchmarks to evaluate the different configuration options of the communication framework ACCL and their impact on communication latency and throughput. Finally, we use our findings to implement a shallow water simulation whose scalability heavily depends on low-latency communication. With a suitable configuration of ACCL, good scaling behavior can be shown to all 48 FPGAs installed in the system. Overall, the results show that the availability of inter-FPGA communication frameworks as well as the configurability of framework and network stack are crucial to achieve the best application performance with low latency communication. Copyright © 2024, The Authors. All rights reserved.

关键词： Field programmable gate arrays (FPGA)

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SWPFOPLD: A Profiling and Optimizing Loader for SW26010Pro Processors 8

SWPFOPLD: A Profiling and Optimizing Loader for SW26010Pro P...

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8th International Conference on computer and Communication Systems, ICCCS 2023

作者： Qian, Hong Wu, Wei Zhu, Qi Wang, Fei Zhao, Jinwei Zheng, Yan School of Computer Science and Technology University of Science and Technology of China Hefei China Jiangnan Institute of Computing Technology System Software Research Department Wuxi China Tsinghua University Department of Computer Science and Technology Beijing China National Research Center of Parallel Computer Engineering and Technology Beijing China

ISBN: (纸本)9781665456128

The Sunway family supercomputers have achieved a series of remarkable achievements. However, the toolchains provided by them are not perfect, which has brought great challenges to the development of high-performance application software. In this paper, a profiling and optimizing tool is proposed to assist people to analyze and optimize the performance of their programs. SWPFOPLD is independent of the application program and gathers the runtime performance data through the PMUs, an automatically hot functions rearrange optimization based on the performance data is furtherly accomplished. The evaluation shows that SWPFOPLD can be easily and effectively used to analyze and optimize the performance of the application programs. © 2023 IEEE.

关键词： Supercomputers

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Scalable quantum detector tomography by high-performance computing

arXiv

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arXiv 2024年

作者： Schapeler, Timon Schade, Robert Lass, Michael Plessl, Christian Bartley, Tim J. Department of Physics Paderborn University Warburger Str. 100 Paderborn33098 Germany Paderborn University Warburger Str. 100 Paderborn33098 Germany Paderborn Center for Parallel Computing Paderborn University Warburger Str. 100 Paderborn33098 Germany Department for Computer Science Paderborn University Warburger Str. 100 Paderborn33098 Germany

At large scales, quantum systems may become advantageous over their classical counterparts at performing certain tasks. Developing tools to analyse these systems at the relevant scales, in a manner consistent with quantum mechanics, is therefore critical to benchmarking performance and characterising their operation. While classical computational approaches cannot perform like-for-like computations of quantum systems beyond a certain scale, classical high-performance computing (HPC) may nevertheless be useful for precisely these characterisation and certification tasks. By developing open-source customised algorithms using high-performance computing, we perform quantum tomography on a megascale quantum photonic detector covering a Hilbert space of 106. This requires finding 108 elements of the matrix corresponding to the positive operator valued measure (POVM), the quantum description of the detector, and is achieved in minutes of computation time. Moreover, by exploiting the structure of the problem, we achieve highly efficient parallel scaling, paving the way for quantum objects up to a system size of 1012 elements to be reconstructed using this method. In general, this shows that a consistent quantum mechanical description of quantum phenomena is applicable at everyday scales. More concretely, this enables the reconstruction of large-scale quantum sources, processes and detectors used in computation and sampling tasks, which may be necessary to prove their nonclassical character or quantum computational advantage. Copyright © 2024, The Authors. All rights reserved.

关键词： Tomography

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computing and Compressing Electron Repulsion Integrals on FPGAs

arXiv

引用

arXiv 2023年

作者： Wu, Xin Kenter, Tobias Schade, Robert Kühne, Thomas D. Plessl, Christian Paderborn Center for Parallel Computing Paderborn University Warburger Str. 100 Paderborn33098 Germany Department of Computer Science Paderborn University Warburger Str. 100 Paderborn33098 Germany Department of Chemistry Paderborn University Warburger Str. 100 Paderborn33098 Germany

The computation of electron repulsion integrals (ERIs) over Gaussian-type orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic simulations. In practical simulations, several trillions of ERIs may have to be computed for every time step. In this work, we investigate FPGAs as accelerators for the ERI computation. We use template parameters, here within the Intel oneAPI tool flow, to create customized designs for 256 different ERI quartet classes, based on their orbitals. To maximize data reuse, all intermediates are buffered in FPGA on-chip memory with customized layout. The pre-calculation of intermediates also helps to overcome data dependencies caused by multi-dimensional recurrence relations. The involved loop structures are partially or even fully unrolled for high throughput of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary bitwidth integers is integrated in the FPGA kernels. To our best knowledge, this is the first work on ERI computation on FPGAs that supports more than just the single most basic quartet class. Also, the integration of ERI computation and compression it a novelty that is not even covered by CPU or GPU libraries so far. Our evaluation shows that using 16-bit integer for the ERI compression, the fastest FPGA kernels exceed the performance of 10 GERIS (10 × 109 ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors around 10−7 - 10−5 Hartree. The measured throughput can be accurately explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform similar computations using the widely used libint reference on a two-socket server with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x. Copyright © 2023, The Authors. All rights reserved.

关键词： Field programmable gate arrays (FPGA)

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Binary Grey Wolf Optimizer for Mapping Real Time Applications on MPSOCs Architecture 7

Binary Grey Wolf Optimizer for Mapping Real Time Application...

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7th International Conference on Informatics and Applied Mathematics, IAM 2024

作者： Boumaza, Farid Zouache, Djaafar Belazzoug, Mouhoub Hadji, Atmane Aroui, Abdelkader Computer Science Department University of Mohamed El Bachir El Ibrahimi Bordj Bou Arreridj34030 Algeria Laboratory of Parallel Embedded architectures and Intensive Computing University of Oran1 Oran31000 Algeria LISI Laboratory Computer Science Department University Center A. Boussouf Mila Mila43000 Algeria Center for Space Techniques Palestine Avenue Arzew Oran31200 Algeria

With the growing complexity of real-time applications, Multi-Processor Systems-on-Chip (MPSoCs) have become a vital solution for meeting stringent performance, power, and scalability requirements. Efficient task mapping plays a crucial role in optimizing the performance of such systems, particularly for real-time applications that demand strict timing constraints. Traditional mapping techniques, including static and dynamic strategies, struggle with balancing execution time, energy efficiency, and communication overhead in heterogeneous MPSoC architectures. In this paper, we propose a novel approach for optimizing task mapping in MPSoCs, based on the Grey Wolf Optimizer (GWO), a bio-inspired metaheuristic renowned for its effectiveness in solving complex optimization problems. This methodology aims to minimize task execution times and communication delays by intelligently mapping real-time tasks onto heterogeneous processing elements (PEs), while also adhering to real-time constraints and reducing energy consumption. The results confirm that the improved GWO algorithm is a powerful tool for addressing the challenges of real-time task mapping in MPSoCs, providing a robust and scalable solution for future embedded systems. © 2024 Copyright for this paper by its authors.

关键词： System-on-chip

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Breaking the Exascale Barrier for the Electronic Structure Problem in Ab-Initio Molecular Dynamics

arXiv

引用

arXiv 2022年

作者： Schade, Robert Kenter, Tobias Elgabarty, Hossam Lass, Michael Kühne, Thomas D. Plessl, Christian Paderborn University Warburger Str. 100 Paderborn33098 Germany Paderborn Center for Parallel Computing Germany Department of Computer Science Germany Department of Chemistry Germany

The non-orthogonal local submatrix method applied to electronic-structure based molecular dynamics simulations is shown to exceed 1.1 EFLOP/s in FP16/FP32 mixed floating-point arithmetic when using 4,400 NVIDIA A100 GPUs of the Perlmutter system. Thi is enabled by a modification of the original method that pushes the sustained fraction of the peak performance to about 80%. Example calculations are performed for SARS-CoV-2 spike proteins with up to 83 million atoms. © 2022, CC BY.

关键词： Electronic structure

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