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Enhanced Path Prediction for Network Resource Management in Wireless LANs

IEEE Wireless Communications 2003年第6期10卷 62-69页

作者： Kyriakakos, Miltiadis Frangiadakis, Nikolaos Merakos, Lazaros Hadjiefthymiades, Stathes University of Athens Department of Informatics Communication Networks Laboratory Greek Consulting Firm Advanced Services Group Ltd. Communication Networks Laboratory University of Athens University of Aegean Dept. of Information Engineering Fac. of the Hellenic Open University Patras Greece Department of Telecommunication University of Maryland College Park Communication Networks Laboratory Department of Informatics University of Athens Fac. of Elec. Eng./Computer Science University of Connecticut Storrs Faculty of Electrical Computer Engineering Department Northeastern University Boston MA Commun./Digit. Proc. Research Center Northeastern University IBM T. J. Watson Research Center Yorktown Heights NY Faculty of the University of Athens Greece Department of of Informatics Communication Network Laboratory Netwk. Oper. and Management Center

Path prediction is currently being considered for use in the context of mobile and wireless computing toward more efficient network resource management schemes. Path prediction allows the network and services to further enhance the quality of service levels the user enjoys. Such mechanisms are mostly meaningful in infrastructures like wireless LANs. In this article we present a path prediction algorithm that exploits the machine learning algorithm of learning automata. The decision of the learning automaton is driven by the movement patterns of a single user but is also affected by the aggregated patterns demonstrated by all users. Simulations of the algorithm, performed using the Realistic Mobility Pattern Generator, show increased prediction accuracy.

关键词： Wireless telecommunication systems

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Dynamic analysis of facial color by using the force feedback system for virtual arm wrestling

Dynamic analysis of facial color by using the force feedback...

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IEEE/ASME International Conference on Advanced Intelligent Mechatronics

作者： Yamada, T Watanabe, T Electronic Mechanical Engineering Department Yuge National College of Maritime Technology 1000 Shimoyuge Yuge-Cho Ochigun 794-2593 Ehime Japan Faculty of Computer Science and System Engineering Okayama Prefectural University CREST Japan Science and Technology 111 Kuboki Soja 719-1197 Okayama Japan

ISBN: (纸本)0780377591

In this paper, we develop a 4-DOF force display system for the analysis by synthesis of facial color for the interaction with anthropomorphic agent. By using the system, we analyze the changes in facial skin temperature and facial color associated with circulation dynamics in response to forced actions. On the basis of the analysis, we propose a synthetic method for the affect display of virtual face with facial color and expression in force display, and the effectiveness of the method is confirmed. Finally, we develop a prototype of virtual arm wrestling system with anthropomorphic agent using synthesized dynamic three-dimensional facial color and expression.

关键词： force display facial skin temperature facial color color image processing virtual face

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A Dickson-type power converter with bootstrapped gate transfer switches

A Dickson-type power converter with bootstrapped gate transf...

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International Conference on Telecommunications Energy (INTELEC)

作者： K. Eguchi Hongbing Zhu T. Tabata F. Ueno Department of Information and Computer Sciences Kumamoto National College of Technology Kumamoto Japan Department of Computer Science Hiroshima Kokusai Gakuin University Hiroshima Japan Department of Electrical System and Computer Engineering Sojo University Kumamoto Japan

In this paper, a Dickson-type power converter with bootstrapped gate transfer switches is proposed. The circuit is designed by adding a polarity exchange circuit and N (N = 2, 3, ...) power-switches to the conventional Dickson-type circuit. These additional circuits enable the converter to provide not only a dc-dc output but a dc-ac output. In the process of dc-ac conversion, the circuit can generate various ac outputs by exploiting pulse amplitude modulation (PAM) method. Furthermore, high efficiency can be achieved by adopting novel bootstrap circuits to power-switches in the converter. Via maximum circuits constructed with diodes, the voltage of forward stage is charged to a capacitor in the bootstrap circuit. By connecting the charged-capacitor between the gate terminals of power-switches and the output terminal of the maximum circuit, the bootstrap circuits reduce the on-resistance of the power-switches. The SPICE simulations for the proposed circuit show the following results: 1. the efficiency of dc-dc conversion is more than 90% when the output load Ro = 500 /spl Omega/ and 2. various types of ac outputs can be generated.

关键词： Switching converters Switches AC generators DC-DC power converters Pulse generation Pulse circuits Pulse modulation Amplitude modulation Diodes Voltage

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A novel dynamic fault restoration mechanism using multiple rings approach in WDM mesh network

A novel dynamic fault restoration mechanism using multiple r...

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Pacific Rim Conference on Lasers and Electro-Optics (CLEO/Pacific Rim)

作者： I-Shyan Hwang I-Feng Huang Chia-Chin Chien Department of Computer Engineering and Science Yuan-Ze University Chungli Taiwan Department of Management Information System Junior College of Nursing Taiwan

ISBN: (纸本)0780377664

This work proposes a distributed algorithm for fault restoration, called the dynamic multiple rings algorithm (DMRA), in a DWDM mesh network. This study explores how to choose restoration paths and distribute a fault-tolerant bandwidth when link, node and channel faults occur. Mesh network topology is becoming increasingly popular, and includes many restoration paths. Calculating the appropriate restoration paths will take a long time if the whole network is considered. Accordingly, the basic idea of this paper is trying to use networking segments near faults to share the restoration load in mesh networks. Each node is responsible for searching restoration paths around it using the proposed DMRA. Nodes use the distributed algorithm to search nearby nodes and establish the relationship between them to build many logical rings. Nodes also can locate the fault in which logical rings are, and these logical rings will establish restoration paths. The traffic load over faulty links or nodes can be diverted to other paths in the networking segments. The cost of restoration paths is computed at each node from both current capacity and transmission time. The selected restoration paths are the appropriate transmission routes in the nearby networks. Accordingly, searching restoration paths and assigning wavelength routings can be performed quickly, depending on network bandwidth and the traffic load. Furthermore, the proposed algorithm is adapted to dynamic networks, and the control messages are to be transmitted in bi-directional control channels. The proposed fault-tolerant mechanism is designed not only for a single fault, but also for multiple faults in the network. Improving the stability and load balance of the network is therefore helpful. Therefore, the method proposed herein can be adopted in a large-scale and complex network topology. The simulation environment employed in this paper is based on the architecture of NFSNet, which includes 14 nodes and 21 links. There

关键词： Wavelength division multiplexing WDM networks Mesh networks Telecommunication traffic Network topology computer architecture Distributed algorithms Fault tolerance Bandwidth Computational modeling

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Design of a step-up/step-down SC DC-DC converter with series-connected capacitors

Design of a step-up/step-down SC DC-DC converter with series...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： K. Eguchi H. Zhu F. Ueno T. Tabata Department of Information and Computer Sciences Kumamoto National College of Technology Kumamoto Japan Department of Computer Science Hiroshima Kokusai Gakuin University Aki Hiroshima Japan Department of Electrical System and Computer Engineering Sojo University Ikeda Kumamoto Japan

A step-up/step-down switched-capacitor (SC) DC-DC converter with series-connected capacitors is proposed in this paper. The circuit can provide more various types of output-voltages than conventional converters, because the series-connected capacitors in a ring-connection enable us to convert an input voltage at short step-up/step-down interval. Furthermore, high efficiency can be achieved by using the power-switches with novel bootstrap circuits. Via maximum circuits constructed with diodes, maximum voltage of the power converter is charged to a capacitor in the bootstrap circuit. By connecting the charged-capacitor between the gate terminals of power-switches and the output terminal of the maximum circuit, the bootstrap circuits reduce the on-resistance of the power-switches. The simulations show that 1) the proposed circuit can realize shorter step-up/step-down interval than the conventional ring-type power converter and 2) the efficiency is more than 95% when the output load R/sub o/=100 /spl Omega/.

关键词： DC-DC power converters Voltage Switched capacitor circuits Clocks Diodes Joining processes Educational institutions computer science systems engineering and theory Computational Intelligence Society

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A new construction of the irreducible polynomial for parallel multiplier over GF(2m)

A new construction of the irreducible polynomial for paralle...

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Thirty-third International Symposium on Multiple-Valued Logic

作者： Hwang, Jong-Hak Moon, Kyung-Jae Park, Seung-Yong Kim, Heung-Soo Dept. of System Engineering Korea Sport Science Institute Incheon Korea Republic of Department of Electronic Engineering Inha University Incheon 402-751 Korea Republic of Dept. of Computer and Info. Eng. Jaenung College Incheon Korea Republic of

This paper presents the construction algorithm of the irreducible polynomial which needs to multiply over GF(2m) and the flow chart representing the proposed algorithm has been proposed. And also, we get the degree from the value of xm-k formation to the value of k = 7 using the proposed flow chart. The multiplier circuit has been implemented by using the proposed irreducible polynomial generation(IPG) algorithm in this paper, and we compared the proposed circuit with the conventional one. In the case of k = 7, one AND gate and five Ex-or gates are needed as the delay time for the irreducible polynomial in the proposed algorithm, but seven AND gates and seven Ex-or gates in the conventional one. As a result, the proposed algorithm shows the improved performance on the delay time.

关键词： Logic circuits

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Approximate aggregate queries with guaranteed error bounds 9th

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9th International Conference on Rough Sets, Fuzzy Sets, Data Mining and Granular Computing, RSFDGrC 2003

作者： Chun, Seok-Ju Lee, Ju-Hong Lee, Seok-Lyong Department of Internet Information Ansan College 752 Il-Dong SangRok-Ku Korea Republic of School of Computer Science and Engineering Inha University 253 YongHyun-dong Nam-Ku Korea Republic of School of Industrial and Information System Engineering Hankuk University of Foreign Studies Yongin-si Korea Republic of

ISBN: (纸本)3540140409

It is very important to provide analysts with guaranteed error bounds for approximate aggregate queries in many current enterprise applications such as the decision support systems. In this paper, we propose a general technique to provide tight error bounds for approximate results to OLAP range-sum queries. We perform an extensive experiment on diverse data sets, and examine the effectiveness of our proposed method with respect to various dimensions of the data cube and query sizes. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Decision support systems

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Mobility and stability evaluation in wireless multi-hop networks using multi-player games 03

Mobility and stability evaluation in wireless multi-hop netw...

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2nd Workshop on Network and system Support for Games, NetGames 2003

作者： Fitzek, F. Badia, L. Zorzi, M. Schulte, G. Seeling, P. Henderson, T. Dipartimento di Ingegneria Universita di Ferrara Via Saragat 1 Ferrara44100 Italy Acticom GmbH Mobile Networks Am Borsigturm 42 Berlin13507 Germany Department of Computer Science University College London Gower Street LondonWC1E 6BT United Kingdom

ISBN: (纸本)1581137346

Multi-hop networks have gained a lot of interest in recent years. A lot of work was contributed in the field of protocol design and performance of multi-hop networks. It is generally accepted that mobility has a huge impact on the protocol performance;even more for multi-hop networks. Obtaining realistic measurements of mobility, however, is complex and expensive. Thus, we adopt virtual world scenarios to explore the mobility issue, by using the well-known multi-player game, Quake II. The advantage of the Quake II engine is that users move within virtual worlds under realistic constraints, whereas other mobility models may offer insuficient accuracy or operate under unrealistic assumptions. Moreover, it is very easy to create new virtual worlds and to adapt them to specialized needs. In this paper, we propose an analytical framework for mobility measurements in virtual worlds that could be adopted for the design of communication protocols. Our framework enables the study of the impact of mobility on connectivity and stability of the network, giving useful insights for improving communication performance. An interesting application of our approach is the analysis of coverage extension of so called hotspots or emergency situations, where the fixed network infrastructure is insuficient or non-existent. In these extreme cases, multi-hop networks can be used to setup communication quickly. As these situations comprise a plethora of different cases and scenarios, our model is appropriate for their analysis, due to its generality. We use our framework to investigate the performance of multi-hop networks based on IEEE 802.11a technology. In contrast to other contributions focusing only on connectivity, the IEEE 802.11a technology also considers multi-rate connections. Our framework covers the evaluation of simple connectivity as well as link quality stability in the presence of mobility, a combination that has not been considered thus far. Therefore we introduce two simple

关键词： Stability

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Orthogonal polynomial method of evolving equivalent cost function of plants with multiple generating units

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Journal of the Institution of Engineers (India): Electrical Engineering Division 2003年第JUN.期84卷 11-15页

作者： Selvi, K. Chitra Selvi, S. Ramaraj, N. Department of Electrical Engineering Madurai 625 015 Tamilnadu India Power System Engineering Madurai 625 015 Tamilnadu India Computer Science and Engineering Thiagarajar College of Engineering Madurai 625 015 Tamilnadu India

This paper presents a method of evolving the equivalent cost functions of plants having multiple generating units. The inequality capacity constraints placed on the units are also taken into account. The use of orthogonal polynomials (OP) will give a very convenient means to obtain the equivalent cost function. This method is sufficiently accurate and easy to implement for real time operation and control of power system. The method does not place any restriction either on the number of plants or on the number of generating units in any plant. The method can be extended directly to evolve the equivalent cost function of plants, in any power system having many areas. The validity of this method is demonstrated with an example system.

关键词： Electric power plants

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A new construction of the irreducible polynomial for parallel multiplier over GF(2/sup m/)

A new construction of the irreducible polynomial for paralle...

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International Symposium on Multiple-Valued Logic

作者： Jong-Hak Hwang Kyung-Jae Moon Seung-Yong Park Heung-Soo Kim Department of System Engineering Korea Sport Science Institute South Korea Department of Electronic Engineering Inha University Incheon South Korea Department of Computer and Information Engineering Jaeneung College Incheon South Korea

ISBN: (纸本)0769519180

This paper presents the construction algorithm of the irreducible polynomial which needs to multiply over GF(2/sup m/) and the flow chart representing the proposed algorithm has been proposed And also, we get the degree from the value of x/sup m.k/ formation to the value of k=7 using the proposed flow chart. The multiplier circuit has been implemented by using the proposed irreducible polynomial generation(IPG) algorithm in this paper, and we compared the proposed circuit with the conventional one. In the case of k=7, one AND gale and five Ex-or gates are needed as the delay time for the irreducible polynomial in the proposed algorithm, but seven AND gales and seven Ex-or gates in the conventional one. As a result, the proposed algorithm shows the improved performance on the delay time.

关键词： Polynomials Signal processing algorithms Delay effects Circuits Galois fields Flowcharts Digital signal processing Very large scale integration Moon systems engineering and theory

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