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2013 4th International Conference on Power Engineering, Energy and Electrical Drives, POWERENG 2013

作者： Colak, Ilhami Kabalci, Ersan Keven, Gokhan Faculty of Technology Department of Electric and Electronic Engineering Gazi University Ankara Turkey Faculty of Engineering and Architecture Dep. of Electrical and Electronic Eng. Nevsehir University Nevsehir Turkey Vocational College of Haci Bektaş Veli Dep. of Computer Programming Nevsehir University Nevsehir Turkey

ISBN: (纸本)9781467363921

The multilevel inverters (MLIs) are classified into three topologies such as Diode Clamped, Flying Capacitor and Cascade Multilevel Inverter (CMLI). CMLI topologies include two kind of structure that is named symmetric and asymmetric topologies. Asymmetric Cascade MLI (ACMLI) topologies consist of unequal DC sources. Many modulation techniques have been used in ACMLI topology such as Multi-Carrier PWM (MC-PWM), Space Vector PWM and Selective Harmonic PWM. The MC-PWM technique is achieved by four different types. In this study, MC-PWM techniques which are named Phase Disposition PWM, Phase Opposition Disposition PWM, Alternate Phase Opposition Disposition PWM and Phase Shifted PWM have been compared. It is uncovered that Phase Opposition Disposition PWM technique is more convenient in terms of Total Harmonic Distortion of output voltage and current signals and in terms of the quality of power factor in ACMLI which is performed in this study. © 2013 IEEE.

关键词： Pulse width modulation

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Reliable System Design with a High Degree of Diagnostic Procedures for Embedded Systems

Reliable System Design with a High Degree of Diagnostic Proc...

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IET Irish Signals and Systems Conference

作者： Michael H. Schwarz Josef Boercsoek Department of Safety Computer Technology University of Kassel Department of Computer Architecture and System Programming University of Kassel

ISBN: (纸本)9781629935881

Maintenance starts with reliable diagnostics. programming Logic Controllers (PLCs) are often equipped with a high degree of diagnostic procedures in order to ensure that the processing unit is functioning correctly. It is vital to verify that the system with its programme is still within a 'healthy' state, otherwise a safety function is called and the system is brought into a safe state, or if possible, defect and malfunctioning components are exchanged during operation and the process can continue without shutting down the system. However, when it comes to smaller devices such as intelligent sensors, embedded controller devices with the functionality of an e.g. PID (Proportional-Integral-Derivative), predictive controller, filter or analytical algorithm, which is embedded into a FPGA or micro-controller then diagnostics and verification methods are often not considered in the way they should be. For example, if an intelligent sensor system is not able to diagnose that the sensor-head is malfunctioning, but the sensor-head still provides some data, then the smart algorithm bases its calculation on wrong data, which can cause a dangerous situation. This paper investigates and shows recent results to combine diagnostic methods for small scale devices. Several safety-related structures are considered with a high degree of diagnostic coverage. The paper presents relevant procedures and structures to increase the reliability of small devices without utilising a full scale microcontroller system.

关键词： Reliability Safety structure Maintenance Diagnosis

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Improving communication in PGAS environments: Static and dynamic coalescing in UPC 13

Improving communication in PGAS environments: Static and dyn...

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27th ACM International Conference on Supercomputing, ICS 2013

作者： Alvanos, Michail Farreras, Montse Tiotto, Ettore Amaral, José Nelson Martorell, Xavier Programming Models Barcelona Supercomputer Center Barcelona Spain Department of Computer Architecture Universitat Politecnica de Catalunya Cr. Jordi Girona 1-3 08034 Barcelona Spain Static Compilation Technology IBM Toronto Laboratory Toronto ON Canada Dep. of Computing Science University of Alberta Edmonton AB Canada Barcelona Supercomputing Center Cr. Jordi Girona 29 08034 Barcelona Spain IBM Canada CAS Research Markham ON Canada

ISBN: (纸本)9781450321303

The goal of Partitioned Global Address Space (PGAS) languages is to improve programmer productivity in large scale parallel machines. However, PGAS programs may have many fine-grained shared accesses that lead to performance degradation. Manual code transformations or compiler optimizations are required to improve the performance of programs with fine-grained accesses. The downside of manual code transformations is the increased program complexity that hinders programmer productivity. On the other hand, most compiler optimizations of fine-grain accesses require knowledge of physical data mapping and the use of parallel loop constructs. This paper presents an optimization for the Unified Parallel C language that combines compile time (static) and runtime (dynamic) coalescing of shared data, without the knowledge of physical data mapping. Larger messages increase the network efficiency and static coalescing decreases the overhead of library calls. The performance evaluation uses two microbenchmarks and three benchmarks to obtain scaling and absolute performance numbers on up to 32768 cores of a Power 775 machine. Our results show that the compiler transformation results in speedups from 1.15X up to 21X compared with the baseline versions and that they achieve up to 63% the performance of the MPI versions. © 2013 ACM.

关键词： Dynamics

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Comparision of Multi-Carrier Techniques in Seven-Level Asymmetric Cascade Multilevel Inverter

Comparision of Multi-Carrier Techniques in Seven-Level Asymm...

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International Conference on Power Engineering, Energy and Electrical Drives

作者： Ilhami COLAK Ersan KABALCI Gokhan KEVEN Faculty of Technology Department of Electric & Electronic Engineering Gazi University Ankara Turkey Faculty of Engineering & Architecture Dep. of Electrical & Electronic Eng. Nevsehir University Nevsehir Turkey Vocational College of Haci Bekta? Veli Dep. of Computer Programming Nevsehir University Nevsehir Turkey

ISBN: (纸本)9781467363914

关键词： asymmetric cascade multilevel inverter multi carrier PWM THD frequency index power factor

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Promoter recognition with machine learning algorithms keREM, RULSE-3 and ANN

Promoter recognition with machine learning algorithms keREM,...

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International Symposium on INnovations in Intelligent SysTems and Applications, INISTA 2012

作者： Karli, Günay Nayir, Ahmet Faculty of Engineering and Information Technology International Burch Universiy Sarajevo Bosnia and Herzegovina Department of Computer Programming Fatih University Istanbul Turkey

ISBN: (纸本)9781467314466

Data mining has become an important and active area of research because of theoretical challenges and practical applications associated with the problem of discovering interesting and previously unknown knowledge from very large real world database. These databases contain potential gold mine of valuable information, but it is beyond human ability to analyze massive amount of data and elicit meaningful patterns by using conventional techniques. In this study, DNA sequence was analyzed to locate promoter which is a regulatory region of DNA located upstream of a gene, providing a control point for regulated gene transcription. In this study, some supervised learning algorithms such as artificial neural network (ANN), RULES-3 and newly developed keREM rule induction algorithm were used to analyse to DNA sequence. In the experiments different option of keREM, RULES-3 and ANN were used, and according to the empirical comparisons, the algorithms appeared to be comparable to well-known algorithms in terms of the accuracy of the extracted rule in classifying unseen data. © 2012 IEEE.

关键词： Supervised learning

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L(0,1)-Labelling of Cactus Graphs

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Communications and Network 2012年第1期4卷 18-29页

作者： Nasreen Khan Madhumangal Pal Anita Pal Department of Applied Mathematics with Oceanology and Computer Programming Vidyasagar University Midnapore India.Department of Applied Mathematics with Oceanology and Computer Programming Vidyasagar University Midnapore India.Department of Mathematics National Institute of Technology Durgapur Durgapur India.

An L(0,1)-labelling of a graph G is an assignment of nonnegative integers to the vertices of G such that the difference between the labels assigned to any two adjacent vertices is at least zero and the difference between the labels assigned to any two vertices which are at distance two is at least one. The span of an L(0,1)-labelling is the maximum label number assigned to any vertex of G. The L(0,1)-labelling number of a graph G, denoted by λ_0.1(G) is the least integer k such that G has an L(0,1)-labelling of span k. This labelling has an application to a computer code assignment problem. The task is to assign integer control codes to a network of computer stations with distance restrictions. A cactus graph is a connected graph in which every block is either an edge or a cycle. In this paper, we label the vertices of a cactus graph by L(0,1)-labelling and have shown that, △-1≤λ_0.1(G)≤△ for a cactus graph, where △ is the degree of the graph G.

关键词： Graph Labelling Code Assignment L(0 1)-Labelling Cactus Graph

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Corrigendum to ‘A single period inventory model with imperfect production and stochastic demand under chance and imprecise constraints’ [Eur. J. Oper. Res. 188 (2008) 121–139]

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European Journal of Operational Research 2013年第3期230卷 703-703页

作者： D. Panda S. Kar K. Maity M. Maiti Department of Engineering Science Haldia Institute of Technology Haldia Purba Medinipur Haldia West Bengal 721 657 India Department of Applied Mathematics with Oceanology and Computer Programming Vidyasagar University Midnapore 721 102 India

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<i>L</i>(0, 1)-Labelling of Cactus Graphs

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Communications and Network 2012年第1期4卷 18-29页

作者： Nasreen Khan Madhumangal Pal Anita Pal Department of Applied Mathematics with Oceanology and Computer Programming Vidyasagar University Midnapore India Department of Mathematics National Institute of Technology Durgapur Durgapur India

An L(0,1)-labelling of a graph G is an assignment of nonnegative integers to the vertices of G such that the difference between the labels assigned to any two adjacent vertices is at least zero and the difference between the labels assigned to any two vertices which are at distance two is at least one. The span of an L(0,1)-labelling is the maximum label number assigned to any vertex of G. The L(0,1)-labelling number of a graph G, denoted by λ0.1(G) is the least integer k such that G has an L(0,1)-labelling of span k. This labelling has an application to a computer code assignment problem. The task is to assign integer control codes to a network of computer stations with distance restrictions. A cactus graph is a connected graph in which every block is either an edge or a cycle. In this paper, we label the vertices of a cactus graph by L(0,1)-labelling and have shown that, △-1≤λ0.1(G)≤△ for a cactus graph, where △ is the degree of the graph G.

关键词： Graph Labelling Code Assignment L(0 1)-Labelling Cactus Graph

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Promoter recognition with machine learning algorithms keREM, RULSE-3 and ANN

Promoter recognition with machine learning algorithms keREM,...

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IEEE International Symposium on Innovations in Intelligent Systems and Applications (INISTA)

作者： Günay Karli Ahmet Nayir Faculty of Engineering and Information Technology International Burch University Sarajevo Bosnia and Herzegovina Department of Computer Programming Fatih University Istanbul Turkey

关键词： Artificial neural networks DNA Classification algorithms Machine learning algorithms Neurons Algorithm design and analysis Biological neural networks

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A dynamic accelerator-cluster architecture

A dynamic accelerator-cluster architecture

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41st International Conference on Parallel Processing Workshops, ICPPW 2012

作者： Rinke, Sebastian Becker, Daniel Lippert, Thomas Prabhakaran, Suraj Westphal, Lidia Wolf, Felix Laboratory for Parallel Programming German Research School for Simulation Sciences 52062 Aachen Germany Department of Computer Science RWTH Aachen University 52062 Aachen Germany Corporate Technology Siemens AG 81739 München Germany Jülich Supercomputing Centre 52428 Jülich Germany MAGMA Giessereitechnologie GmbH 52072 Aachen Germany

ISBN: (纸本)9780769547954

Accelerators such as graphics processing units (GPUs) provide an inexpensive way of improving the performance of cluster systems. In such an arrangement, the individual nodes of the cluster are directly connected to one or more accelerator devices via PCI Express. This results in a static mapping of accelerators onto compute nodes, where each accelerator can only be accessed from exactly one compute node. While this static mapping enables efficient data transfers between a given accelerator and the compute node it belongs to, differing computational demands across jobs may, however, produce either underutilized accelerators or nodes whose computational demands cannot be satisfied with the number of accelerators available to them. In particular, smaller numbers of GPUs available per node may enforce explicit MPI parallelism across compute nodes where it is not necessary. To address this limitation, we propose a novel accelerator-cluster architecture in which network-attached accelerators are dynamically assigned to compute nodes. This allows not only their optimal utilization but also a more precise match between application requirements and accelerator hardware. We outline the general concept of our dynamic architecture and show that it can offer substantial benefits to certain classes of applications without significantly harming the performance of others. © 2012 IEEE.

关键词： Memory architecture

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