In order to increase the channel capacity of CDMA (code division multiple access) mobile and personal communicationsystems, a new time diversity CDMA scheme that employs orthogonal modulation is proposed. The time di...
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In order to increase the channel capacity of CDMA (code division multiple access) mobile and personal communicationsystems, a new time diversity CDMA scheme that employs orthogonal modulation is proposed. The time diversity CDMA scheme with orthogonal modulation reduces the required Eb/(No+Io) by 5 dB at Pe = 10/sup -2/ in Rayleigh fading environments with fDT (the product of Doppler frequency and one symbol duration) values ranging from 0.002 to 0.02. This improvement in required Eb/(No+Io) significantly increases the channel capacity of CDMA communicationsystems that have time varying channels. computer simulation results show that the required time delay values of the time diversity scheme are resonably short (20-100 symbols for 10 kbps transmission) for fDT values ranging from 0.002 to 0.02.
Accuracy requirements are usually determined as a percentage of the specification range of the measured part or process. Setting accuracy requirements in this manner results in a wide and unpredictable range of false ...
Accuracy requirements are usually determined as a percentage of the specification range of the measured part or process. Setting accuracy requirements in this manner results in a wide and unpredictable range of false rejection and acceptance probabilities. This causes extra costs due to either: 1) over specification of measurement systems accuracy requirements;2) time, effort, retesting, and resolution of false rejections;or 3) system degradation caused by false acceptance of out-of-specification parts. Achieving a consistent and known risk of false acceptance is only possible by considering the measured process C(pk), the process's mean in relation to the center of the specification range, and the measurement system error distribution. This paper presents a method for calculating the probabilities of false rejection and false acceptance for a normal process which is measured with, alternately, uniform and normally distributed error. It is shown that under most conditions uniform error causes 20% to 30% higher false rejection and acceptance probabilities. Thus, knowledge of measurement error distribution could provide lower total production cost.
An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r≥s, a design o...
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An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a des...
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An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a design of an s-stage PRPG capable of producing 2/sup s/-1 distinct r-bit patterns within 2/sup s/-1 clock pulses independent of the hardware realization of the PRPG. For the case when r >
Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the sp...
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Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the space-time compressor technique for the case when responses from N chips on the board are wired to the compressor; and the time compressor technique for the case when test responses from each chip are transferred to the compressor via system bus. Assuming a single-faulty-chip model, a faulty chip on the board under test is located by an analysis of the relationship between the distortions in the obtained signatures. Both techniques for board-level diagnosis require less hardware than the straightforward diagnostic techniques using a built-in signature analyzer for every chip or selective testing of each chip via the system bus, hence offering an efficient approach for a design of a built-in-self-test board for for manufacturing testing.< >
The paper presents performance results for the SHINPADS serial data bus operating in the environment of a modern, frigate-class ship using a combination of point-to-point links for certain major applications systems a...
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The paper presents performance results for the SHINPADS serial data bus operating in the environment of a modern, frigate-class ship using a combination of point-to-point links for certain major applications systems and the shared, SHINPADS bus for others. The traffic model used is representative of experience in the design of new ships of this type. It is shown that the bus has adequate performance for the expected traffic load. In addition it is shown that, as traffic increases, delay problems will show up in the application processor environment before there is any significant degradation of the performance of the bus. The value of the provision of several classes of priority on the bus is also investigated.
This book constitutes the refereed proceedings of the 6th International Conference on Convergence and Hybrid Information Technology, ICHIT 2012, held in Daejeon, Korea, in August 2012. The 94 revised full papers prese...
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ISBN:
(数字)9783642326455
ISBN:
(纸本)9783642326448
This book constitutes the refereed proceedings of the 6th International Conference on Convergence and Hybrid Information Technology, ICHIT 2012, held in Daejeon, Korea, in August 2012. The 94 revised full papers presented were carefully reviewed and selected from 196 submissions. The papers are organized in topical sections on communications and networking; HCI and virtual reality; image processing and pattern recognition; hardware design and applications; computational biology and medical information; data mining and information retrieval; security and safety system; software engineering; workshop on advanced smart convergence (IWASC).
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