Despite numerous advantages of 3-D integrated circuits (ICs), their commercial success remains limited. In part, this is due to the wide availability of trustworthy intellectual property (IP) blocks developed for 2-D ...
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Driven by worldwide demands for renewable energy source, photovoltaic (PV) inverters, which are the most important part for energy conversion, have seen a considerable amount of innovations in recent years. The trends...
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ISBN:
(纸本)9781467343541
Driven by worldwide demands for renewable energy source, photovoltaic (PV) inverters, which are the most important part for energy conversion, have seen a considerable amount of innovations in recent years. The trends for PV inverters are toward high efficiency, high reliability, low ground leakage current, low-output ac-current distortion, and reactive power capability. This paper provides an efficiency optimized design of an Auxiliary Resonant Snubber with Coupled-Magnetic Reset Zero-voltage switching (ZVS) inverter for PV application. The main device is Power MOSFETs, which have low conduction loss and could achieve ZVS in all load condition. The auxiliary devices are low current, low cost IGBTs and Diodes, which could achieve zero-current switching (ZCS). To achieve high efficiency, resonant circuit is analyzed to optimally design the resonant components, which is based on the guarantee of full range ZVS, gating delay-time design, and lower power loss in auxiliary circuit. The power loss model is also analyzed to select suitable power device and further improve the efficiency. At last, experiment results of a 5kW single phase inverter in PV system was presented, which has more than 99% CEC efficiency and work in full load condition without cooling fan. Besides, reactive power capability is also demonstrated.
In this paper, we consider the problem of minimizing the total transmission cost for exchanging channel state information. We proposed a network coded cooperative data exchange scheme, such that the total transmission...
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To date, different techniques of navigation for mobile robots have been developed. However, the experimentation of these techniques is not a trivial task because usually it is not possible to reuse the developed contr...
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Many embedded systems must satisfy timing requirements, which describe how these systems should behave with respect to timing. Such requirements must be dealt with throughout the system development process: from their...
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A system consisting of n components connected in a circular manner is called a circular consecutive-κ-out-of-n: F system if it fails when κ or more consecutive components fail. One of the most important problems for...
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MR images have been used extensively in clinical trials in recent years because they are harmless to the human body and can obtain detailed information by scanning the same slice with various frequencies and parameter...
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The RSA cryptographic algorithm is a security tool that has achieved long cryptographic and market maturity. However, after the discovery and wide spread of Side Channel Attacks (SCA), RSA implementations are suscepti...
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The RSA cryptographic algorithm is a security tool that has achieved long cryptographic and market maturity. However, after the discovery and wide spread of Side Channel Attacks (SCA), RSA implementations are susceptible to a variety of different attacks that target the hardware structure rather than the algorithm itself. While there are a wide range of countermeasures that can be applied on the RSA structure in order to protect the algorithm from specific SCA categories, combining several such measures to produce an "all in one" SCA resistant RSA structure is not an easy endeavor. Several incompatibility issues between combined SCA protection methods lead to new SCA vulnerabilities. In this paper, we evaluate some very popular and potent SCAs against RSA, like Fault attacks (FA), Simple Power attacks (SPA), Doubling attacks (DA) and Differential Power attacks (DPA), and propose an SCA protection scheme for RSA based on Chinese Remainder Theorem (CRT) that can thwart them. The proposed scheme uses a square and always multiply approach in combination with the message blinding technique in such a way that possible vulnerabilities that may rise from this combination can no longer apply. The proposed scheme is evaluated against specific SCAs and is found to be very secure. From performance point of view, the proposed scheme favors parallelism and can calculate an RSA result with small time delay.
RSA cryptographic algorithm has long achieved cryptographic and market maturity. However, RSA implementations, after the discovery of Side Channel Attacks (SCA), are susceptible to a variety of different attacks that ...
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RSA cryptographic algorithm has long achieved cryptographic and market maturity. However, RSA implementations, after the discovery of Side Channel Attacks (SCA), are susceptible to a variety of different attacks that target the hardware structure rather than the algorithm itself. There are a wide range of countermeasures that can be applied on the RSA structure in order to protect the algorithm from SCAs, however few of them are efficient in hardware since they add extensive performance cost to an SCA resistant RSA implementation. In this paper, a hardware architecture is proposed based on a Fault attack (FA) and Simple Power attack (SPA) resistant algorithm for Chinese Remainder Theorem (CRT) RSA that through the principles of parallelism and component reusability can guarantee hardware efficiency. We describe an implementation approach based on Montgomery modular multiplication and also propose a testing hardware architecture to simulate the security chip environment that our FA-SPA resistant CRT RSA can be integrated in. The designed architecture is implemented in FPGA technology and results on its time and space complexity are extracted and evaluated.
Formats for describing timing behaviors range from fixed menus of standard patterns, to fully open-ended behavioral definitions;of which some may be supported by formal semantic underpinnings, while others are better ...
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