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Security-aware VLSI design for speaker identification based on efficient SMO architecture

Security-aware VLSI design for speaker identification based ...

引用

International Conference on Awareness Science and Technology (iCAST)

作者： Jhing-Fa Wang Jr-Shiang Peng Po-Chuan Lin Bo-Wei Chen Nai-Sheng Shihi Department of Electrical Engineering National Cheng Kung University Tainan Taiwan Department of Electronics Engineering and Computer Science Tung-Fang Design University Kaohsiung Taiwan

ISBN: (纸本)9781457708879

Speaker identification is a popular investigation that is greatly applied in many applications such as human-machine interfaced, security systems, etc. In real life, low cost and fast response are both necessary features for speaker identification in stand-alone embedded device. However, most of the responding time occupies in training phase, and the cost of general solution by employing digital signal processors is too high. In this work, security-aware VLSI design with the efficient Sequential Minimal Optimization (SMO) architecture is proposed for solving the problems in text-independent speaker identification. Our contributions are attributed to the optimal VLSI design form algorithm to architecture level. At algorithm level, the proposed Improved SMO (ISMO) algorithm is adopted for efficient data selection and it can reduce 30% computation. At architecture level, a distributed and reconfigurable computing architecture which combines parallel and pipeline designing styles is implemented, and it provides the high flexible and high performance benefits. Finally, the experimental results show that the proposed design can save 50% of memory usage, and the hardware resources can be reduced by 31% than our previous work. Furthermore, the responding time can decrease 85%.

关键词： computer architecture Very large scale integration

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WEC prototype advancement with consideration of a real-time damage accumulation algorithm

WEC prototype advancement with consideration of a real-time ...

引用

Power Tech Conference

作者： Chad J. Stillinger Ted K. A. Brekken Annette von Jouanne Robert Paasch David Naviaux Ken Rhinefrank Joseph Prudell Al Schacher Erik Hammagren Department of Electrical Engineering and Computer Science Northwestern University Mechanical Design in the School of Mechanical Industrial and Manufacturing Engineering at Oregon State University USA

Machine maintenance and repair is not a trivial issue when it comes to renewable energy devices. It has been said that one of the most important factors in enhancing the marketability of wind energy is to cut its overall maintenance costs, which is about 10% - 20% of the overall cost of energy. The average maintenance and repair costs of ocean wave energy devices are yet to be determined, but it may be higher than wind energy. The harsh ocean environment, repeated cycling of the drive train, coastal storms, environmental concerns, loss of revenue due to long periods of machine downtime, safety issues concerning technicians working on the buoy while it's still in operation, and so forth, all add to the maintenance and repair costs of a WEC (Wave Energy Converter). This study proposes a unique damage accumulation prediction algorithm that enables real-time determination of bearing fatigue life.

关键词： Mathematical model Equations Stress Loading Maintenance engineering Torque Generators

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Human-robot interaction based on cloud computing infrastructure for senior companion

Human-robot interaction based on cloud computing infrastruct...

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IEEE Region 10 International Conference TENCON

作者： Yan-You Chen Jhing-Fa Wang Po-Chuan Lin Po-Yi Shih Hsin-Chun Tsai Da-Yu Kwan Department of Electrical Engineering National Cheng Kung University Tainan Taiwan Department of Electronics Engineering and Computer Science Tung-Fang Design University Kaohsiung Taiwan

ISBN: (纸本)9781457702563

This paper presents a human-robot interactive system for senior companion based on cloud computing infrastructure. The proposed senior companion robot system (SCRS) is designed based on cloud computing network. In the server side, two cloud services are proposed, 1) the web-based user remote management service (WURMS) for remote robot control; 2) the robotic multimodal interactive computation services (RMICS) for providing the human-robot operation interfaces including the speech/sound recognition, speaker identification, face identification, sound source estimation and text to speech (TTS). In the robot client side, the behavior model is designed to use WURMS and RMICS services. In the experiments, two robots called “Robert” and “Davinci” are designed to evaluate the SCRS's capability. With using only low-cost and low-power CPUs (Intel Atom N450), both of the two robots can still work wirelessly for real-time human-robot interaction. Finally, we design five senior companion scenarios, and the experimental average MOS (Mean Opinion Score) is 4.16.

关键词： Thyristors Robot sensing systems Speech recognition Speech Cloud computing Face

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A component based architecture to improve testability, targeted FPGA-based vision systems

A component based architecture to improve testability, targe...

引用

International Conference on Communication Software and Networks, ICCSN

作者： Mostafa Pordel Nima Moghaddami Khalilzad Farahnaz Yekeh Lars Asplund Department of Computer Science Umeå University Umea Sweden School of Innovation Design and Engineering Mälardalen University Vasteras Sweden

FPGA has been used in many robotics projects for real-time image processing. It provides reliable systems with low execution time and simplified timing analysis. Many of these systems take a lot of time in development and testing phases. In some cases, it is not possible to test the system in real environments very often, due to accessibility, availability or cost problems. This paper is the result of a case study on vision systems for two robotics projects in which the vision team consisted of seven students working for six months fulltime on developing and implementing different image algorithms. While FPGA has been used for real-time image processing, some steps have been taken in order to reduce the development and testing phases. The main focus of the project is to integrate different testing methods with FPGA development. It includes a component based solution that uses a two-way communication with a PC controller for system evaluation and testing. Once the data is acquired from the vision board, the system stores it and simulates the same environment that has been captured earlier by feeding back the obtained data to FPGA. This approach addresses and implements a debugging methodology for FPGA based solutions which accelerate the development phase. In order to transfer massive information of images, RMII which is an interface for Ethernet communication, has been investigated and implemented. The provided solution makes changes easier, saves time and solves the problems mentioned earlier.

关键词： Field programmable gate arrays Robots Process control Monitoring Switches Clocks Reliability

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SSTKR: Secure and Testable Scan design through Test Key Randomization

SSTKR: Secure and Testable Scan Design through Test Key Rand...

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Asian Test Symposium (ATS)

作者： Mohammed Abdul Razzaq Virendra Singh Adit Singh Computer Design and Test Lab Indian Institute of Science Bangalore India Department of Electrical Engineering Aubum University Auburn USA

Scan test is the standard method, practiced by industry, that has consistently provided high fault coverage due to high controllability and high observability. The scan chain allows to control and observe the internal signals of a chip. However, this property also facilitates hackers to use scan architecture as a means to breach chip security. This paper addresses this issue by proposing a new method called Secure and testable Scan design through Test Key Randomization(SSTKR). SSTKR is a key based method to prevent hackers from stealing secret information. Linear Feedback Shift Register (LFSR) is used to generate authentication keys to be embedded in test vectors. Unique key is used for every test vector which prevents scan based side channel attacks effectively. Any attempt to steal secret information will lead to a randomized response. SSTKR has very low area and test time overhead without performance penalty. Our approach also facilitates in-field test of the chip.

关键词： Vectors Authentication computer hacking Testing Logic gates Observability

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Modular equivalence verification of polynomial datapaths with multiple word-length operands

Modular equivalence verification of polynomial datapaths wit...

引用

IEEE International High-Level design Validation and Test Workshop

作者： Bijan Alizadeh Masahiro Fujita Electrical and Computer Engineering Department University of Tehran Iran VLSI Design and Education Center (VDEC) CREST University of Tokyo Japan

In this paper, we extend Modular Horner Expansion Diagram (Modular-HED) as a canonical polynomial representation to verify polynomial functions with multiple bit-width operands from Z 2n1 ×Z 2n2... ×Z 2nd to Z 2n . Our contributions are mostly in efficient implementation of [1] with a canonical decision diagram in such a way that both verification and synthesis of large arithmetic circuits can be more efficient. The experimental results show the effectiveness of our approach in comparison with other decision diagrams and algebraic techniques.

关键词： Polynomials Boolean functions Computational modeling Data structures Vectors Optimization Hardware

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FPGA implementation of real-time Ethernet communication using RMII interface

FPGA implementation of real-time Ethernet communication usin...

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International Conference on Communication Software and Networks, ICCSN

作者： Nima Moghaddami Khalilzad Farahnaz Yekeh Lars Asplund Mostafa Pordel School of Innovation Design and Engineering Mälardalen University Vasteras Sweden Department of Computer Science Umeå University Umea Sweden

FPGA-based solutions have become more common in embedded systems these days. These systems need to communicate with external world. Considering high-speed and popularity of Ethernet communication, a reliable real-time Ethernet component inside FPGA is of special value. To that end, this paper presents a new solution for 100 Mb/s FPGA-based Ethernet communications with timing analysis. The solution deals with "Reduced Media-Independent Interface" in its physical layer. UDP is the network protocol which is implemented from physical to transport layer. For getting used in real-time applications, timing analysis is done in the communication system. Component based software engineering is used in the design and development processes. In order to test the components inside FPGA, two different approaches are utilized. Signal measurement in combination with introduced windows based application contributes much in testing and validation phases.

关键词： Clocks Equations Complexity theory Field programmable gate arrays

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Operational mode exploration for reconfigurable systems with multiple applications

Operational mode exploration for reconfigurable systems with...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Stefan Wildermann Felix Reimann Jürgen Teich Zoran Salcic Hardware/Software Co-Design University of Erlangen-Nuremberg Germany Department of Electrical and Computer Engineering University of Auckland New Zealand

Modern embedded systems incorporate multiple applications that run on the same execution platform. However, due to limited resources and other constraints, not all the combinations of applications may run concurrently. This paper tackles the problem of determining which combinations of applications can run on a given hardware architecture without violating given constraints, thus creating feasible operational modes of the system. The architecture itself may include standard processors for software implementation of applications and dynamically (partially) reconfigurable hardware resources, which enable dynamic sharing of the resource in different operational modes. The paper describes the models, theoretical results, and the mode exploration algorithm to perform this task. Here, the specification is symbolically encoded so that the feasibility of modes can be tested by applying a SAT solver. In the experiment, we demonstrate how to apply our approach to build a self-organizing smart camera framework.

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The future of advanced driving assistance system development in China

The future of advanced driving assistance system development...

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IEEE International Conference on Vehicular Electronics and Safety (ICVES)

作者： Lian Duan Fang Chen Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden Interaction Design Department of Apply IT Chalmers University of Technology Gothenburg Sweden

Nowadays, with the rapid development of vehicle industry in China, an increasing number of companies realized the importance of culture adaption, when implementing ADAS (Advanced Driving Assistance System) to the vehicles in China. However, some designing issues of these systems need to be solved, taking consideration of driver's behavior and traffic situation in China. There is a lack of studies on Chinese drivers and related to HMI design of ADAS systems in the literature. There are limited reports on Chinese traffic and drivers studies, but still lack of the necessary depth. Some interaction design methodologies, including personas, focus group study, questionnaire and so on, were used in these reports. However, these studies are neither intensive nor comprehensive. Although (part of) the issues are brought up and analyzed, only general solutions are mentioned for the designing of the systems. Present paper, through literature review, indicated different areas that need to be focused on that are related to culture issues and the possible methodologies that can be applied.

关键词： Vehicles Roads Accidents Safety Cultural differences Monitoring Europe

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RTL delay macro-modeling with Vt and Vdd variability

RTL delay macro-modeling with Vt and Vdd variability

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International design and Test Workshop

作者： Tatsuya Koyagi Sohaib Majzoub Masahiro Fukui Resve Saleh Department of VLSI System Design Ritsumeikan University Siga Japan Department of Electrical and Computer Engineering American University Dubai Dubai UAE Department of Electrical and Computer Engineering University of British Columbia BC Canada

Recent low-power design utilizes a variety of approaches for V dd and V t control to reduce dynamic and leakage power. It is important to be able to explore various low-power design options at a high-level early in the design process. Furthermore, process variation is becoming large and greatly affects the power and delay results. In particular, the delay analysis becomes very complicated and time-consuming with existing tools. This paper proposes a new efficient RTL delay macro-model to address these recent problems. The goal is to provide transistor-level accuracy at the RTL level with V t and V dd variability. It also includes the ability to handle PVT variations. The validation of the model is demonstrated by comparison with a circuit simulator and a timing verification tool. The experiments show this macro-model predicts the delay for variable V dd and V t with an accuracy of ±5% against HSPICE™ and ±10% against PrimeTime™ for a number of ITC'99 benchmark circuits.

关键词： Delay Integrated circuit modeling Mathematical model Threshold voltage Logic gates Equations Benchmark testing

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