This study describes the development to date of a computational full-body human phantom based on the VHP female dataset. Its unique feature is full compatibility both with MATLAB and specialized FEM computational soft...
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This study describes the development to date of a computational full-body human phantom based on the VHP female dataset. Its unique feature is full compatibility both with MATLAB and specialized FEM computational software packages such as ANSYS HFSS/Maxwell 3D. Applications for low-frequency and radio-frequency electromagnetic modeling are considered.
The current trend of growth of information reveals that it is inevitable that large-scale learning problems become the norm. In this paper, we propose and analyze a novel Low-density Cut based tree Decomposition metho...
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ISBN:
(纸本)9781479943012
The current trend of growth of information reveals that it is inevitable that large-scale learning problems become the norm. In this paper, we propose and analyze a novel Low-density Cut based tree Decomposition method for large-scale SVM problems, called LCD-SVM. The basic idea here is divide and conquer: use a decision tree to decompose the data space and train SVMs on the decomposed regions. Specifically, we demonstrate the application of low density separation principle to devise a splitting criterion for rapidly generating a high-quality tree, thus maximizing the benefits of SVMs training. Extensive experiments on 14 real-world datasets show that our approach can provide a significant improvement in training time over state-of-the-art methods while keeps comparable test accuracy with other methods, especially for very large-scale datasets.
Modular multiplication is the most crucial component in RSA cryptosystem. In this paper, we present a new modular multiplication architecture using the Strassen multiplication algorithm and Montgomery reduction. The a...
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Modular multiplication is the most crucial component in RSA cryptosystem. In this paper, we present a new modular multiplication architecture using the Strassen multiplication algorithm and Montgomery reduction. The architecture is different from the interleaved version of Montgomery multiplication traditionally used in RSA design. By selecting different bases of 16 or 24 bits, it could perform 8,192-bit or 12,288-bit modular multiplication. The design was synthesized on the Altera's Stratix-V FPGA using Quartus II. It performs one modular multiplication in 2,030 cycles. When operating at 209 MHz, the execution time for an 8K- or 12K-bit modular multiplication is about 9.7 μs.
Most stereovision applications are binocular which uses information from a 2-camera array to perform stereo matching and compute the depth image. Trinocular stereovision with a 3-camera array has been proved to provid...
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Power dissipation of bioamplifiers has become one of the most critical factors for up-to-date implantable neural recording microsystems as the increasing of recording channels. This paper presents an ultra-low-power b...
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Stochastic Rotation Dynamics (SRD) is a novel particle-based simulation method that can be used to model complex fluids [1], [2], such as binary and ternary mixtures [3], and polymer solutions [4]-[6], in either two o...
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Stochastic Rotation Dynamics (SRD) is a novel particle-based simulation method that can be used to model complex fluids [1], [2], such as binary and ternary mixtures [3], and polymer solutions [4]-[6], in either two or three dimensions. Although SRD is efficient compared to traditional methods, it is still computationally expensive for large system sizes, e.g. when using a large array of particles to simulate dense polymer solutions. Recently, as the power offered by Graphics Processing Units (GPUs) has risen, General Purpose GPU (GPGPU) computing has been introduced as an effective way to improve performance for parallel computation tasks. This work focuses on the acceleration of SRD simulations using Nvidia's GPGPU architecture, CUDA. We find that while the speed improvements delivered by GPU acceleration vary with the simulation version and parameters used, our GPU implementation runs around 10 times faster than the CPU version for basic simulations, and up to 50 times faster for polymers in solution.
This paper compares interference alignment and opportunistic transmission for a 3-user single-input single-output (SISO) interference channel in terms of average sum rate in the presence of channel estimation errors. ...
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This paper compares interference alignment and opportunistic transmission for a 3-user single-input single-output (SISO) interference channel in terms of average sum rate in the presence of channel estimation errors. In the case of interference alignment, channel estimation errors cause interference leakage which consequently results in a loss of achievable rate. In the case of opportunistic transmission, channel estimation errors result in a non-zero probability of incorrectly choosing the node with the best channel. The effect of these impairments is quantified in terms of the achievable average sum rate of these transmission techniques. Analysis and numerical examples for independent and identically distributed fading channels show that SISO interference alignment can achieve better average sum rate with good channel estimates and at high SNR whereas opportunistic transmission provides better performance at low SNR and/or when the channel estimates are poor.
This paper presents a design technique for generation of GHz ADC sampling clock phases from a low-cost low-frequency clock source. Jitter of order 0.1ps is enabled using a DLL-based frequency multiplication method. No...
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This paper presents a design technique for generation of GHz ADC sampling clock phases from a low-cost low-frequency clock source. Jitter of order 0.1ps is enabled using a DLL-based frequency multiplication method. Nonidealities of the DLL approach are mitigated through digital background correction. Simulated results in a 180nm CMOS process are presented.
Drivers' failure to observe traffic signs, especially the stop signs, has led to many serious traffic accidents. Video-based traffic sign detection is an important component of driver-assistance systems. In earlie...
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Drivers' failure to observe traffic signs, especially the stop signs, has led to many serious traffic accidents. Video-based traffic sign detection is an important component of driver-assistance systems. In earlier systems, simple color and shape-based detection methods have been broadly applied. Recently, feature-based traffic sign detection algorithms are proposed to obtain more accurate results, especially when combined with the previous two. The Speeded Up Robust Features (SURF) algorithm is an outstanding feature detector and descriptor with rotation and illumination invariance. Unfortunately, due to its computational complexity, the application of SURF algorithm remains limited in real-time systems. In this paper, we present a real-time SURF-based traffic sign detection system by exploiting parallelism and rich resources in FPGAs. The proposed hardware design is able to accurately process video streams of 800 × 600 resolution at 60 frame per second.
The random demodulator architecture is a compressive sensing based receiver that allows the reconstruction of frequency-sparse signals from measurements acquired at a rate below the signal's Nyquist rate. This in ...
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ISBN:
(纸本)9781479900657
The random demodulator architecture is a compressive sensing based receiver that allows the reconstruction of frequency-sparse signals from measurements acquired at a rate below the signal's Nyquist rate. This in turn results in tremendous power savings in receivers because of the direct correlation between the power consumption of analog-to-digital converters (ADCs) in communication receivers and the sampling rate at which these ADCs operate. In this thesis, we propose design techniques for a robust and efficient random demodulator. The resetting mechanism can pose challenges in practical settings that can degrade the performance of the random demodulator. We propose practical approaches to mitigate the effect of resetting and propose resetting schemes that provide robust performance.
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