A performance evaluation has been carried out by simulation experiments for a three priority CEBus router handling traffic between the PL and TP media. The message and channel throughput, and message and packet delay ...
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A performance evaluation has been carried out by simulation experiments for a three priority CEBus router handling traffic between the PL and TP media. The message and channel throughput, and message and packet delay have been studied for a wide range of offered traffic loads. The router has behaved well, according to message priority. The inter-network traffic has showed larger delay than intra-network traffic.
Two different object-oriented modeling approaches, DEVS and EMSY, constitute the background to explore the area of variable structure modeling. The realization of various kinds of structural changes is discussed in bo...
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This paper describes a high-speed D/A conversion system with an embedded 5-bit programmable FIR filtering function suitable for applications in video interfaces. For demonstration purposes a prototype chip has been fa...
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In this paper we discuss a mixed-mode architecture for implementation of artificial neural networks (ANNs). This type of architecture is suitable for applications in the areas of nonlinear control and audio signal pro...
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In this paper we discuss a mixed-mode architecture for implementation of artificial neural networks (ANNs). This type of architecture is suitable for applications in the areas of nonlinear control and audio signal processing. Synapses are built with a switched-capacitor multiplying D/A converter (MDAC) and a pseudo 4Q analog multiplier. The multiplier inputs are voltages while its output is a current, The analog weight value is stored in a capacitor. The MDAC front-end is included with each synapse for D/A conversion and periodic on-chip refreshment of the capacitor charge. Neurons are built with MOS transistors exploiting the quadratic characteristics of the saturation region. A CMOS prototype chip was designed and fabricated for demonstration of the proposed architecture.
In this paper the Supervisory Control Problem (SCP) for discrete event systems (DES) is generalized to a class of probabilistic discrete event systems (PDES). Necessary and sufficient conditions for the existence of a...
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In this paper the Supervisory Control Problem (SCP) for discrete event systems (DES) is generalized to a class of probabilistic discrete event systems (PDES). Necessary and sufficient conditions for the existence of a solution to the probabilistic SCP for a class of nonterminating PDES are developed. Methods of representing probabilistic supervisors for PDES are described and the computation of supervisors is briefly discussed. Finally, we discuss how the results may be extended to terminating probabilistic languages.< >
An alternative recycling two-step flash analog-digital converter architecture is presented where the concurrent operation of two multiplying digital-analog converters (MDACs) with a single flash quantizer yields an im...
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An alternative recycling two-step flash analog-digital converter architecture is presented where the concurrent operation of two multiplying digital-analog converters (MDACs) with a single flash quantizer yields an improved throughput rate over the traditional architecture. The effects of subpath mismatches in the overall converter performance are estimated. A design example is given to demonstrate its feasibility.< >
Extensions of conventional multirate switched capacitor (SC) polyphase networks are developed, yielding efficient SC circuits for two-dimensional analog filtering with finite impulse response. The proposed new circuit...
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Extensions of conventional multirate switched capacitor (SC) polyphase networks are developed, yielding efficient SC circuits for two-dimensional analog filtering with finite impulse response. The proposed new circuits offer the advantages of systematic design procedures and reduced silicon area for integrated circuit implementation. A simple design example corresponding to a 3 /spl times/ 3/finite impulse response (FIR) filter is presented.< >
A novel technique is presented for electrical programmability of switched capacitor biquadratic sections based on the concept of charge-programmability realized using digitally-programmable quasi-passive circuits. Som...
A novel technique is presented for electrical programmability of switched capacitor biquadratic sections based on the concept of charge-programmability realized using digitally-programmable quasi-passive circuits. Some examples of filtering functions found in practical telephone signaling applications are discussed. The technique can achieve a high degree of programmability with much less capacitor area than would be required using currently available programming techniques.< >
A design technique is described for the realization of a digital-to-analog (D/A) conversion system with an embedded finite impulse response (FIR) filtering function suitable for the compensation of the sin x/x distort...
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A design technique is described for the realization of a digital-to-analog (D/A) conversion system with an embedded finite impulse response (FIR) filtering function suitable for the compensation of the sin x/x distortion introduced by fully sampled-and-held signals and which is attractive for integrated circuit implementation from the viewpoints of area and power consumption. This is demonstrated for an 8-b D/A conversion prototype system with an associated 3-tap 5-b precision FIR filtering function that has been fabricated using a 1.2-/spl mu/m digital CMOS technology.< >
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