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CAD CAM MANUFACTURING OF PROTOTYPE SHIPBOARD components

NAVAL ENGINEERS JOURNAL 1990年第3期102卷 93-99页

作者： CALVERT, TE RODRIGUEZ, FA SLEBZAK, JS Thomas E. Calvert P.E.: is a senior project engineer with the Propulsion and Auxiliary Systems Department David Taylor Research Center Annapolis Md. His interests include application of computers to all aspects of engineering with particular emphasis on utilization of small computers. Mr. Calvert is a licensed professional engineer in Maryland. He received a BSEE from Drexel University in 1969 and since that time has completed a number of graduate courses related to machinery acoustics. Francisco A. Rodriguez:is an engineer with the Propulsion and Auxiliary Systems Department David Taylor Research Center. He was formerly with the Computer-Aided Design/Interactive Graphics Group of the Division of Engineering and Weapons U.S. Naval Academy. His interests include interfacing the computer aided design to the computer aided manufacturing along with related software and hardware development. Mr. Rodriguez received a BSEEfrom the University of Virginia in 1968. James S. Slebzak:is a mechanical engineering technician with the Propulsion and Auxiliary Systems Department David Taylor Research Center. He received his machinists papers in 1971 after serving his apprenticeship at David Taylor Research Center. He continued his education and became the senior numerical control programmer at the Annapolis Laboratory. He completed his mechanical technology degree from Anne Arundel Community College in 1986. His interests are in the application of numerically controlled manufacturing techniques to prototype machinery components.

The machine shop at the Annapolis Laboratory of the David Taylor Research Center (DTRC) provides model making and prototype support to a large variety of naval ship related engineering projects. In order to meet these challenging requirements, computer aided design/computer aided manufacturing (CAD/CAM) techniques are being used to produce “one of a kind” prototypes or very low volume production parts. The use of computer aides in these cases is to facilitate the accurate manufacture of a difficult part, rather than to improve manufacturing efficiencies. In addition, the approach provides the flexibility required to support research and development projects. Several examples of prototype shipboard components manufactured using CAD/CAM techniques are presented in this paper. The hardware and software that facilitated these projects are discussed. The examples described have met the requirements to produce a wide variety of prototype shipboard machinery components quickly and accurately.

关键词： Ship Equipment

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COMPARING BARRIER ALGORITHMS

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PARALLEL COMPUTING 1989年第2期12卷 157-170页

作者： ARENSTORF, NS JORDAN, HF Computer Systems Design Group Department of Electrical and Computer Engineering University of Colorado Boulder CO 80309 U.S.A.

A barrier is a method for synchronizing a large number of concurrent computer processes. After consideration of some basic synchronization mechanisms, a collection of barrier algorithms with either linear or logarithmic depth will be presented. A graphical model is described that profiles the execution of the barriers and other parallel programming constructs. This model shows that in order to achieve the best performance, different situations call for different barrier implementations. Timing experiments supporting these conclusions are detailed.

关键词： Barrier graphical model MIMD computer shared memory speedup synchronization

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Large-Scale Optimal Power Flow: Effects of Initialization, Decoupling & Discretization

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IEEE Power engineering Review 1989年第5期9卷 72-74页

作者： Papalexopoulos, Alex D. Imparato, Carl F. Wu, Felix F. Systems Engineering Group Pacific Gas and Electric Company San Francisco California United States Department of Electrical Engineering and Computer Sciences University of California Berkeley California United States

This paper presents the results of extensive numerical testing of a second-order OPF solution method. The testing was conducted using a 1500 bus network under various loading conditions. Three issues were studied: ° Sensitivity of the solution with respect to the initial conditions ° Accuracy of decoupling the original OPF problem into separate active power and the reactive power OPF problems ° Effects of the discretization of transformer taps on solutions. Copyright © 1989 by The Institute of electrical and Electronics Engineers, Inc.

关键词： Large-scale systems Load flow Medical services Power systems Power system modeling Voltage System testing Reactive power Power system control Circuit breakers

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Design and implementation of an integrated voice, data, and video services network

Design and implementation of an integrated voice, data, and ...

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IEEE Pacific Rim Conference on Communications, computers and Signal Processing

作者： D.W. Jacobson Computer Systems Research Group Department of Electrical and Computer Engineering Iowa State University Ames IA USA

The design issues in implementing an integrated voice, data, and video services system on a token ring network are discussed. The presence of real-time traffic, namely voice, on the same network makes the implementation complicated. The performance requirements of these traffic types are different. Voice creates stream traffic on a network, whereas data traffic is bursty. Voice packets need to be delivered within a limited time interval, whereas the data emphasizes error-free delivery. A possible solution, supported by a simulation study, is discussed.< >

关键词： Telecommunication traffic Protocols Token networks Facsimile Stochastic processes computer networks Traffic control Bandwidth Delay estimation Jacobian matrices

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A high-speed, byte-serial, multiple-bus interconnection network

A high-speed, byte-serial, multiple-bus interconnection netw...

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IEEE Pacific Rim Conference on Communications, computers and Signal Processing

作者： W.J. Armstrong A.V. Pohm J.A. Davis Computer Systems Research Group Department of Electrical and Computer Engineering Iowa State University Ames IA USA

A research project at Iowa State University to investigate the use of a high-speed, byte-serial bus to implement a multiple-bus interconnection network for a fine-grain parallel architecture is discussed. The project focuses on the electrical properties of the bus, high-speed serial transmission, and bus contention resolution. Prototypes were developed to test critical aspects of the design, and the network was simulated to analyze its performance within the context of the parallel architecture. Results indicate that the network can effectively interconnect many processors (64) with relatively few buses (5), thereby giving a low packplane line count. By making a uniform bus that sent bytes at a rate limited only by clock skew, it was possible to increase the information transmission rate on a line by a factor of 4-10 over a conventional bus. This allowed for several high-speed buses with a limited pin count. It is concluded that multiple-bus networks offer the connectivity and bandwidth of a crossbar switch at a reasonable implementation cost.< >

关键词： Multiprocessor interconnection networks Parallel architectures Switches Virtual prototyping Testing Analytical models Context modeling Performance analysis Clocks Bandwidth

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Physical design of testable VLSI: Techniques and experiments

Physical design of testable VLSI: Techniques and experiments

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11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89

作者： Levitt, Marc E. Abraham, Jacob A. Computer Systems Group Coordinated Science Lab. University of Illinois 1101 W. Springfield Ave. UrbanaIL 61801 United States Department of Electrical and Computer Engineering University of Texas at Austin Austin TX 78712 United States

Static CMOS circuits can fail in ways that make the traditional stuck-at fault model and test generation techniques inadequate. It will be shown that the layout of these circuits can affect testability and in some cases reduce the number of possible faults in a design. A method is presented to analyze circuits at the symbolic layout level and to enhance testability using local transformations. A set of standard cells was designed using the layout level techniques. These standard cells are used in the MIS synthesis system to design over 100 example circuits. It is shown that the modified designs enable stuck-at tests to achieve significantly higher stuck-open fault coverage with an overhead that can be easily estimated. A synthesis strategy is presented to design easily testable random logic circuits. © 1989 IEEE.

关键词： computer circuits

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Automatic Generation of Behavioral Models from Switch-Level Descriptions

Automatic Generation of Behavioral Models from Switch-Level ...

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Design Automation Conference

作者： D.T. Blaauw D.G. Saab R.B. Mueller-Thuns J.A. Abraham J.T. Rahmeh Computer Systems Group University of Illinois Urbana IL USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

This paper discusses the automatic generation of high-level software models from switch-level circuit descriptions. The proposed algorithms operate directly on the hierarchical description, and incorporate information about the design such as the structure, regularity, functionality, and control signals in the generation process. New algorithms are proposed and have been implemented for combinational modules and bus structures. A significant speedup has been obtained for these modules of a commercially available chip.

关键词： Circuit simulation Very large scale integration Partitioning algorithms Permission Switching circuits Signal design Automatic generation control Signal generators Equations Registers

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An electromechanically scanned microstrip antenna for airborne applications

An electromechanically scanned microstrip antenna for airbor...

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Antennas and Propagation Society International Symposium

作者： C.D. Massey F. Lalezari D.J. McLaughlin R.E. McIntosh Ball Communications Systems Group Broomfield CO USA Electrical and Computer Engineering Department University of Massachusetts Amherst MA USA

The authors describe a frequency-scanned microstrip array antenna developed for the University of Massachusetts' airborne C-band scatterometer system. The antenna is a linearly polarized array consisting of 16 series-fed E-plane columns each with 27 microstrip patch radiating elements. A schematic of the antenna radiating surface is presented, and frequency-scanned radiation patterns are shown.< >

关键词： Microstrip antennas Microstrip antenna arrays Frequency Shafts Radar antennas Optical fiber cables Power cables Application software Airplanes Azimuth

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Modeling the atmosphere as an unguided optical communications channel

Modeling the atmosphere as an unguided optical communication...

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IEEE International Conference on Communications (ICC)

作者： R.M. Nuber K.S. Shanmugan TRW Electronics Systems Group Redondo Beach CA USA Department of Electrical and Computer Engineering University of Kansas Lawrence KS USA

The authors propose a system-level model for simulating the Earth's atmosphere as an unguided optical communications channel. The major degradations in received optical intensity introduced by the atmosphere are scintillation, beam spreading, beam wander, and atmospheric transmissivity. The model presented considers scintillation and beam wander to impose random fading in the received signal while beam spreading is a constant loss in intensity. Atmospheric transmissivity is treated as a filterlike channel transfer function. Relationships for the parameters of the model are given in terms of parameters which characterize the optical link. Also included is a description of an implementation of the model. The implementation discussed is being integrated into an end-to-end simulator for a direct-detention laser communication system operating in the atmosphere.< >

关键词： Atmospheric modeling Communication channels Degradation Optical receivers Optical transmitters Optical filters Optical fiber communication Terrestrial atmosphere Optical propagation Laser modes

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A novel approach to accurate timing verification using RTL descriptions 89

A novel approach to accurate timing verification using RTL d...

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Proceedings of the 26th ACM/IEEE Design Automation Conference

作者： K. Roy J. A. Abraham Computer Systems Group Coordinated Science Laboratory University of IIlinois at Urbana-Champaign Urbana IL Department of Electrical and Computer Engineering University of Texas at Austin Austin TX

ISBN: (纸本)9780897913102

Timing verification is a critical part of VLSI circuit design. A new approach to timing verification using Register Transfer Level (RTL) descriptions is presented, which eliminates false paths that occur due to (i) redundancy, (ii) reconvergent fanout or (iii) control signal constraints, and generates a test for the critical paths. High level instructions of the circuit are used to test for any timing violations. An algorithm to identify a minimal set of instructions that tests the circuit for all timing errors in valid paths is proposed. Results are presented based on an implementation of the algorithm in LISP programming language on a TI Explorer machine.

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