Intracellular processes triggered by neural activity include changes in ionic concentrations, protein release, and synaptic vesicle cycling. These processes play significant roles in neurological disorders. The benefi...
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The rapid proliferation of Internet of Things (IoT) devices has posed significant challenges for network resource allocation and management. In this paper, we propose a novel methodology for efficient resource allocat...
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In the rapidly evolving field of Augmented Reality (AR), delivering real-time, immersive experiences places a significant demand on computational resources, particularly in the context of video-based Artificial Intell...
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Sleep is vital for wellness, and electroencephalography (EEG) serves as an instrumental tool in the study of sleep. Sleep is classified into four stages: stages N1-N3, and rapid eye movement (REM). To acquire effectiv...
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ISBN:
(数字)9798350371499
ISBN:
(纸本)9798350371505
Sleep is vital for wellness, and electroencephalography (EEG) serves as an instrumental tool in the study of sleep. Sleep is classified into four stages: stages N1-N3, and rapid eye movement (REM). To acquire effective and robust EEG features for sleep detection and analysis, we explore the dimensionality reduction effects of Uniform Manifold Approximation and Projection (UMAP) on various features of the EEG signals. Compared with traditional band power analysis, UMAP demonstrated higher accuracy for sleep stage classification and better reliability. Using UMAP, we observed an average of 11% increase in accuracy and an average of 20% increase in Macro-F1 Score on the same dataset. Particularly, in the wakefulness stage, Macro-F1 Score increased by 23%. Moreover, the 2D visual analysis revealed the outstanding ability of UMAP to cluster EEG signals after significant dimensionality reduction of the data.
One-class classification aims to learn one-class models from only in-class training samples. Because of lacking out-of-class samples during training, most conventional deep learning based methods suffer from the featu...
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Test-time adaptation (TTA) fine-tunes pre-trained deep neural networks for unseen test data. The primary challenge of TTA is limited access to the entire test dataset during online updates, causing error accumulation....
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The phenomenon of urbanization in Indonesia is inevitable. The new residential and economic centers in suburban areas is also a problem in city development. The gradual planning and development of smart cities in a li...
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Measuring statistical properties of network traffic can improve our understanding of traffic distribution and help us detect short and long-term anomalies. However, computing the exact value of these properties requir...
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ISBN:
(数字)9798350380385
ISBN:
(纸本)9798350380392
Measuring statistical properties of network traffic can improve our understanding of traffic distribution and help us detect short and long-term anomalies. However, computing the exact value of these properties requires significant storage and computation, which limits their application in high-speed networks. Hardware accelerators provide the computational power to process a large sequence of network packets with high throughput and low latency, but their performance is ultimately limited by the amount of on-chip memory available on the device. Consequently, researchers have proposed sketch-based algorithms to estimate properties of a data stream with sub linear memory and theoretical estimation error bounds. In this paper, we present a streaming algorithm and hardware accelerator for quantile estimation, which is based on the architecture of the KLL sketch. Implemented on an AMD Virtex XCU55 UltraScale+ FPGA, the accelerator operates at a clock frequency of 356 MHz, thereby achieving a minimum line rate of 182 Gbps and a maximum estimation latency of 4.33 µs. When processing a set of 10 real traffic traces of up to 123 million packets, the accelerator estimates 1000 packet-size quantiles per trace with a median error of 0.39% or less, and a maximum error of 1.3% or less across all traces.
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