A general model for traffic flows on packet-switched, virtual-circuit based, fixed-packet networks is introduced, and an exact schedulability test is obtained for systems of such flows. Rules are derived that make the...
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A general model for traffic flows on packet-switched, virtual-circuit based, fixed-packet networks is introduced, and an exact schedulability test is obtained for systems of such flows. Rules are derived that make the evaluation of this schedulability test feasible and efficient under certain circumstances. The practical relevance of this approach is demonstrated by applying it to a number of standard traffic models.
Memory protection is an important OS feature for the reliability and safety of real-time control systems. In this paper, we study the feasibility of memory protection in small embedded systems in which memory size ran...
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Memory protection is an important OS feature for the reliability and safety of real-time control systems. In this paper, we study the feasibility of memory protection in small embedded systems in which memory size ranges from several tens of KBytes to several hundreds of KBytes. We evaluate various protection methods in terms of memory consumption, processing overhead, multiple-thread support, region enlargement, and hardware support. We present a new protection method called intermediate-level skip multi-size paging which skips unused intermediate-level page tables of multi-level paging and supports several page sizes. Our evaluation results show that this method along with paged segmentation and short-circuit segment tree are more cost-effective than other known memory protection methods. Also, the feasibility of intermediate-level skip multi-size paging can be improved if a MMU supporting several page sizes is available for microprocessors.
In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling alg...
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In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling algorithms to prioritize the transmission of the queued packets. Due to the high-speed links and small packet sizes, a hardware solution is needed for the priority queue in order to make the link schedulers effective. But for good performance, the switch should also support a large number of priority levels (P) and be able to buffer a large number of packets (N). So a hardware priority queue design must be both fast and scalable (with respect to N and P) in order to be implemented effectively. In this paper we first compare four existing hardware priority queue architectures, and identify scalability limitations on implementing these existing architectures for large N and P. Based on our findings, we propose two new priority queue architectures, and evaluate them using simulation results from Verilog HDL and Epoch implementations.
This paper considers the problem of rescheduling in a decentralized manufacturing system, Flexible manufacturing systems must be able to respond to unexpected disruptions, including schedule disruptions, However, when...
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This paper considers the problem of rescheduling in a decentralized manufacturing system, Flexible manufacturing systems must be able to respond to unexpected disruptions, including schedule disruptions, However, when a cell controller in a decentralized system responds to a disruption, it may disrupt some other cell, because the actions taken at one cell may have some consequence at another cell, In the approach we propose, a controller at a disrupted cell tries to respond in a way which is likely to be least disruptive to other cells, through negotiation with controllers at other cells, This approach, which we call ''polite replanning,'' has the advantage of retaining much of any original distributed plan, while avoiding wide propagation of the disruption through the rest of the system, We apply this concept to the domain of distributed factory rescheduling, and describe PRIAM (polite rescheduler for intelligent automated manufacturing), a ''polite'' rescheduling architecture which is currently under development, Simulation results show that the use of negotiation in ''polite'' rescheduling prevents the wide propagation of disruption from an initial local disruption.
ALOHA scheme with dynamic time Division Duplexed (TDD) transmission is designed and analyzed. A centralized (i.e., star) network is adopted as the topology of a cell which consists of a base station and a number of mo...
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ALOHA scheme with dynamic time Division Duplexed (TDD) transmission is designed and analyzed. A centralized (i.e., star) network is adopted as the topology of a cell which consists of a base station and a number of mobile clients. In dynamic TDD transmission mode, a channel is time-shared for downlink and uplink transmissions under the dynamic access control of the base station. We first propose two MAC protocols (called TDD1 and TDD2) depending on how downlink and uplink transmissions are multiplexed. We then analyze throughput and average delay of TDD1 and an alternative ALOHA scheme using Frequency Division Duplexed (FDD) transmission. Finally, we evaluate the performance of these schemes, and compare TDD1 (calculations), TDD2 (simulations), and FDD (calculations). TDD schemes are found to always work as good as, or better than, FDD. TDD2 is observed to outperform TDD1 with respect to the downlink delay in the presence of light uplink and heavy downlink traffic loads while they work almost the same in other cases.
EMERALDS (Extensible Microkernel for Embedded Real time Distributed Systems) is a real time microkernel designed for cost conscious small to medium size embedded systems. It not only offers standard OS services like m...
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Parallel machines have the potential to satisfy the large computational demands of emerging real-time applications. These applications require a predictable communication network, where time-constrained traffic requir...
ISBN:
(纸本)9780897917865
Parallel machines have the potential to satisfy the large computational demands of emerging real-time applications. These applications require a predictable communication network, where time-constrained traffic requires bounds on latency or throughput while good average performance suffices for best-effort packets. This paper presents a router architecture that tailors low-level routing, switching, arbitration and flow-control policies to the conflicting demands of each traffic class. The router implements deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay for time-constrained traffic, while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traffic, the router shares packet buffers and link-scheduling logic between the multiple output ports. Verilog simulations demonstrate that the design meets the performance goals of both traffic classes in a single-chip solution.
This paper deals with two important concerns in decentralized control: (1) communication over field bus and (2) the transition from a single powerful, centralized controller to many smaller, distributed controllers. T...
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This paper deals with two important concerns in decentralized control: (1) communication over field bus and (2) the transition from a single powerful, centralized controller to many smaller, distributed controllers. The former requires real-time network scheduling for the field bus to ensure that messages get delivered in a timely manner, while the latter requires a low-overhead real-time operating system to cater to the specific needs of distributed control. We present solutions to both of these problems in the form of a network scheduling scheme for the controller area network (CAN) field bus and the EMERALDS real-time operating system which we have designed with the needs of the decentralized control application designer in mind.
EMERALDS (Extensible Microkernel for Embedded Real time Distributed Systems) is a real time microkernel designed for cost conscious small to medium size embedded systems. It not only offers standard OS services like m...
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EMERALDS (Extensible Microkernel for Embedded Real time Distributed Systems) is a real time microkernel designed for cost conscious small to medium size embedded systems. It not only offers standard OS services like multi threaded processes, real time scheduling, protected address spaces, message passing, semaphores, and timers, but does so in an efficient manner while keeping the kernel size to just tens of kilobytes. For efficiency, EMERALDS uses the novel approach of mapping the kernel into each user level address space, so even with full memory protection, system calls do not need context switches unless a user level server is involved. EMERALDS also provides the flexibility for users to add communication protocol stacks and device drivers as user level servers without modifying the kernel. We have completed a uniprocessor version of EMERALDS for the Motorola 68040 processor whose size is under 13 KBytes. Context switch takes under 12 /spl mu/s and system calls have overhead just 1.8 /spl mu/s more than that of simple subroutine calls.
In any distributed system, messages must be ordered according to their cause-and-effect relation to ensure correct behavior of the system. Causal ordering is also essential for services like atomic multicast and repli...
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In any distributed system, messages must be ordered according to their cause-and-effect relation to ensure correct behavior of the system. Causal ordering is also essential for services like atomic multicast and replication. In distributed real-time systems, not only must proper causal ordering be ensured, but message deadlines must be met as well. Previous algorithms which ensure such behavior include the /spl Delta/-protocol family and the MARS approach. However, both these algorithms give large response times by delaying all messages for a fixed period of time. In this paper we show that for small- to medium-sized real-time systems (consisting of a few tens of nodes) as are commonly used for embedded applications, it becomes feasible to extend the h-protocol so that instead of delaying all messages for a fixed period, each message is delayed according to its deadline. Our algorithm requires certain message deadlines to be adjusted by the application designer and we show that for small-scale applications such as those used in embedded systems, this adjustment is feasible and can be automated by the use of proper CAD tools.
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