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International Conference on European Electricity Market, EEM

作者： Emmanouil A. Bakirtzis Andreas V. Ntomaris Evaggelos G. Kardakos Christos K. Simoglou Pandelis N. Biskas Anastasios G. Bakirtzis Power Systems Laboratory Department of Electrical & Computer Engineering Aristotle University of Thessaloniki Thessaloniki Greece Aristotle University of Thessaloniki Thessaloniki GR

This paper presents a unified unit commitment and economic dispatch tool for the short-term scheduling of a power system under high renewable penetration. The proposed model uses variable time resolution and scheduling horizon extended up to 36 hours ahead and produces robust real-time decisions making the short-term operation of the power system almost insensitive to RES forecast errors. The proposed model is tested for a monthly period on the Greek interconnected power system using real load and wind power data for two different wind penetration levels. Simulation results show that the proposed methodology allows for the accommodation of large amounts of wind energy into the short-term scheduling of the power system at minimum cost.

关键词： Wind forecasting Wind power generation Power systems Load modeling Real-time systems Scheduling Economics

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A new balanced-to-single-ended (BTSE) power divider

A new balanced-to-single-ended (BTSE) power divider

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2014 IEEE International Wireless Symposium, IWS 2014

作者： Wu, Lin-Sheng Guo, Yong-Xin Qiu, Liang-Feng Mao, Jun-Fa Key Laboratory of Ministry of Education of Design and EMC of High-Speed Electronic Systems Shanghai Jiao Tong University Shanghai 200240 China Department of Electrical and Computer Engineering National University of Singapore Singapore 117576 Singapore Research Institute Suzhou City 215123 Jiangsu Province China

ISBN: (纸本)9781479934034

A balanced-to-single-ended (BTSE) power divider is proposed in this paper. Its input is a differential pair while both the outputs are single-ended ports. It can replace the cascade of a balun and a conventional power divider. The characteristics requirements of a two-way BTSE power divider with equal power division are first derived, and then a prototype is designed for 2.0 GHz. In order to construct the component compactly, a short-ended four-wire coupled line and T-shaped sections are utilized to realize a -90° transmission line and a phase inverter, respectively. The developed prototype occupies an area of 0.077 λg2, where λg is the guided wavelength of central frequency. It provides all the desired performances within the operating bandwidth of 25%, with low insertion loss and good balance also achieved. © 2014 IEEE.

关键词： Timing circuits

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Automated web service composition supporting conditional branch structures

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Enterprise Information systems 2014年第1期8卷 121-146页

作者： Wang, Pengwei Ding, Zhijun zhijun_ding@*** Jiang, Changjun Zhou, Mengchu Department of Computer Science and Technology Tongji University Shanghai 201804 China Key Laboratory of “Embedded System and Service Computing” Ministry of Education Shanghai 201804 China Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 USA

The creation of value-added services by automatic composition of existing ones is gaining a significant momentum as the potential silver bullet in service-oriented architecture. However, service composition faces two aspects of difficulties. First, users' needs present such characteristics as diversity, uncertainty and personalisation; second, the existing services run in a real-world environment that is highly complex and dynamically changing. These difficulties may cause the emergence of nondeterministic choices in the process of service composition, which has gone beyond what the existing automated service composition techniques can handle. According to most of the existing methods, the process model of composite service includes sequence constructs only. This article presents a method to introduce conditional branch structures into the process model of composite service when needed, in order to satisfy users' diverse and personalised needs and adapt to the dynamic changes of real-world environment. UML activity diagrams are used to represent dependencies in composite service. Two types of user preferences are considered in this article, which have been ignored by the previous work and a simple programming language style expression is adopted to describe them. Two different algorithms are presented to deal with different situations. A real-life case is provided to illustrate the proposed concepts and methods. [ABSTRACT FROM AUTHOR]

关键词： conditional branch structure control construct service composition user preference web service

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A hardware implementation of Hough Transform based on parabolic duality

A hardware implementation of Hough Transform based on parabo...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Naren Ramesh George Purdy Carla Purdy Justin Smith Dept. of Electrical Engineering & Computing Systems University of Cincinnati Cincinnati OH USA Computer Science Department Northern Kentucky University Highland Heights KY USA

The Hough Transform is a pattern recognition tool commonly used in many image processing algorithms for detecting straight lines. Hough's original formulation of this transform, based on Cartesian coordinates, could not detect vertical lines, and thus it has become common to use Duda and Hart's approach, based on the Radon Transform, which uses polar coordinates and trigonometric functions. For a hardware implementation, this typically requires the use of CORDIC algorithms or lookup tables, thus adding overhead and reducing precision. In this paper we show that Hough's original method, slightly modified, competes well with the Radon transform formulation in terms of speed and required resources in an FPGA implementation. The architecture of our design is straightforward. And because it is implemented in Verilog on an FPGA, the design can also easily be tuned to the desired accuracy.

关键词： Transforms Field programmable gate arrays Algorithm design and analysis Random access memory Hardware computer architecture Accuracy

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Decoding of Intentional Actions from Scalp Electroencephalography (EEG) in Freely-behaving Infants

Decoding of Intentional Actions from Scalp Electroencephalog...

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Annual International Conference of the IEEE engineering in Medicine and Biology Society

作者： Zachery R. Hernandez Jesus Cruz-Garza Teresa Tse Jose L. Contreras-Vidal Non-Invasive Brain-Machine Interface Systems Laboratory at the Department of Electrical and Computer Engineering University of Houston (UH) Center for Robotics and Intelligent Systems Tecnologico de Monterrey

ISBN: (纸本)9781424479276

The mirror neuron system (MNS) in humans is thought to enable an individual's understanding of the meaning of actions performed by others and the potential imitation and learning of those actions. In humans, electroencephalographic (EEG) changes in sensorimotor a-band at central electrodes, which desynchronizes both during execution and observation of goal-directed actions (i.e., μ suppression), have been considered an analog to MNS function. However, methodological and developmental issues, as well as the nature of generalized μ suppression to imagined, observed, and performed actions, have yet to provide a mechanistic relationship between EEG μ-rhythm and MNS function, and the extent to which EEG can be used to infer intent during MNS tasks remains unknown. In this study we present a novel methodology using active EEG and inertial sensors to record brain activity and behavioral actions from freely-behaving infants during exploration, imitation, attentive rest, pointing, reaching and grasping, and interaction with an actor. We used δ-band (1-4Hz) EEG as input to a dimensionality reduction algorithm (locality-preserving Fisher's discriminant analysis, LFDA) followed by a neural classifier (Gaussian mixture models, GMMs) to decode the each MNS task performed by freely-behaving 6-24 month old infants during interaction with an adult actor. Here, we present results from a 20-month male infant to illustrate our approach and show the feasibility of EEG-based classification of freely occurring MNS behaviors displayed by an infant. These results, which provide an alternative to the μ-rhythm theory of MNS function, indicate the informative nature of EEG in relation to intentionality (goal) for MNS tasks which may support action-understanding and thus bear implications for advancing the understanding of MNS function.

关键词： Electroencephalography Scalp Acceleration Training Coherence Electrodes Testing

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Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs

Understanding the tradeoffs between software-managed vs. har...

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IEEE International Symposium on Performance Analysis of systems and Software

作者： Chao Li Yi Yang Hongwen Dai Shengen Yan Frank Mueller Huiyang Zhou Department of Electrical and Computer Engineering North Carolina State University Department of Computing Systems Architecture NEC Laboratories America Institute of Software North Carolina State University Department of Computer Science North Carolina State University

On-chip caches are commonly used in computer systems to hide long off-chip memory access latencies. To manage on-chip caches, either software-managed or hardware-managed schemes can be employed. State-of-art accelerators, such as the NVIDIA Fermi or Kepler GPUs and Intel's forthcoming MIC “Knights Landing” (KNL), support both software-managed caches, aka. shared memory (GPUs) or near memory (KNL), and hardware-managed L1 data caches (D-caches). Furthermore, shared memory and the L1 D-cache on a GPU utilize the same physical storage and their capacity can be configured at runtime (same for KNL). In this paper, we present an in-depth study to reveal interesting and sometimes unexpected tradeoffs between shared memory and the hardware-managed L1 D- caches in GPU architecture. In our study, the kernels utilizing the L1 D-caches are generated from those leveraging shared memory to ensure that the same optimizations such as tiling are applied equally in both versions. Our detailed analyses reveal that rather than cache hit rates, the following tradeoffs often have more profound performance impacts. On one hand, the kernels utilizing the L1 caches may support higher degrees of thread-level parallelism, offer more opportunities for data to be allocated in registers, and sometimes result in lower dynamic instruction counts. On the other hand, the applications utilizing shared memory enable more coalesced accesses and tend to achieve higher degrees of memory-level parallelism. Overall, our results show that most benchmarks perform significantly better with shared memory than the L1 D-caches due to the high impact of memory-level parallelism and memory coalescing.

关键词： Graphics processing units Tiles Kernel Prefetching computer architecture Parallel processing

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Joint optimal placement and energy allocation of underwater sensors in a tree topology

Joint optimal placement and energy allocation of underwater ...

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Annual Conference on Information Sciences and systems (CISS)

作者： Hadis Dashtestani Paul Cotae Ira S. Moskowitz Department of Electrical and Computer Engineering University of the District of Columbia Washington DC USA Naval Research Laboratory Center for High Assurance Computer Systems Washington DC USA

By using the Karush-Kuhn-Tucker (KKT) conditions in a multi-hop hierarchical tree structure we obtained the optimal placement of the underwater acoustic sensor nodes with respect to the capacity of the wireless links between the nodes. We assumed that the energy consumption of each sensor node is constant. We were able to calculate the vertical and horizontal distances between each sensor nodes and also between any levels of interest. On the same tree topology we focused on the energy efficient transmission in underwater sensor networks by providing the optimal transmitting energies for the nodes with fixed locations.

关键词： Resource management Capacitive sensors Wireless sensor networks Wireless communication Topology Energy efficiency

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Impact of geometry aspect ratio on 10-nm gate-all-around silicon-germanium nanowire field effect transistors

Impact of geometry aspect ratio on 10-nm gate-all-around sil...

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IEEE Conference on Nanotechnology

作者： Pei-Jung Chao Yiming Li Parallel and Scientific Computing Laboratory National Chaio Tung University Hsinchu Taiwan Department of Electrical and Computer Engineering National Chaio Tung University Hsinchu Taiwan

In this paper, we study electrical characteristics of gate-all-around (GAA) silicon-germanium (SiGe) nanowire field effect transistors (NWFETS) with different aspect ratio (AR) of channel. Device characteristics: the subthreshold swing (SS), the drain induced barrier lowering (DIBL), and the I ON /I OFF ratio are simulated by using three-dimensional quantum mechanically corrected device simulation. electrical characteristics of 10-nm-gate GAA Si 1-x Ge x NWFET devices are explored with respect to different thickness of SiGe and Ge's mole fraction. It is investigated that an ellipse-shaped channel with a small aspect ratio possesses better DC characteristics, compared with the one which has large AR due to its good gate controllability.

关键词： Logic gates Computational modeling Silicon Mathematical model Field effect transistors Solid modeling Electric variables

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Performance Comparisons of Programs in Different Programming Languages Converted from Legacy Finite Element Codes

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Journal of electrical engineering 2014年第5期2卷 213-220页

作者： Thiruchelvam Arudchelvam Samuel Ratnajeevan Herbert Hoole Department of Computing and Information Systems Faculty of Applied Sciences Wayamba University of Sri Lanka Kuliyapitiya60200 Sri Lanka Department of Electrical and Computer Engineering Michigan State University East Lansing M148824-1226 USA

The FORTRAN programming language was used in early days of writing finite element field computation to write programs Much of those codes were developed in an ad hoc way. Today, modem software developers face problems in understanding, modifying and utilizing those codes. As modem software engineers are very concerned with object oriented design, if those codes are converted into an object oriented language, they could be redesigned and deployed in an object oriented system. Those legacy codes often need to be converted not only into an object oriented programming language such as Java but also into functional oriented languages such as C. Conversion of those legacy codes into modem languages gives many advantages. The purpose of this paper is to compare the performances of such converted legacy finite element codes originally written in FORTRAN, the relevant converted C program and Java program. Sample finite element programs written in FORTRAN are converted for purposes of comparison into modem languages such as C and Java. Performances are compared based on the execution time. In addition to that, the memory sizes of the execution file of FORTRAN and C programs are also compared. Java being interpretive there is no execution file to compare.

关键词： Finite element method legacy software performance evaluation re-engineering.

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ANN-based DTC scheme to improve the dynamic performance of an IM drive

ANN-based DTC scheme to improve the dynamic performance of a...

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7th IET International Conference on Power Electronics, Machines and Drives, PEMD 2014

作者： Bouhoune, K. Yazid, K. Boucherit, M.S. Power and Industrial Systems Laboratory Faculty of Electronics and Computer Science University of Science and Technology Houari Boumediene PO Box 32 El Alia Bab Ezzouar 16111 Algiers Algeria Process Control Laboratory Department of Electrical Engineering Polytechnic National School PO Box 182 10 Hassan Badi El-Harrach 16200 Algiers Algeria

ISBN: (纸本)9781849198158

In addition to simplicity, the DTC of the IM allows a good torque control in steady-state and transient operating conditions. However, high torque ripple is produced, which is reflected in speed estimation responses. It also increases acoustical noise and makes the voltage source inverter operated in high and variable switching frequency, requiring a high sampling frequency. In this paper, a simple effective ANN-based DTC of the induction machine is proposed. Neural networks with a simple architecture are designed and implemented in influential points of the direct torque control block of the three phase induction machine in order to improve its dynamic performance while preserving the DTC structure simplicity as much as possible. In particular, this paper proposes to reduce, on the one hand, the torque ripple and commutation frequency. Neural comparators are used to select the appropriate bandwidth for the torque and flux hysteresis controllers. Their aim is to optimize the ripple level in the developed torque and flux. On the other hand, a neural speed controller is designed in order to improve the system ability to respond rapidly to changes in process variables and mitigate the effects of external perturbations. The performance of the proposed control are tested in simulation and highlighted by comparing to the conventional DTC control based on conventional hysteresis comparators and conventional PI speed controller. The obtained results show the feasibility and good performances of the proposed control.

关键词： Neural networks

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