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Wavelet-based multiresolutional representation of computational field simulation datasets 97

Wavelet-based multiresolutional representation of computatio...

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Proceedings of the 8th conference on Visualization '97

作者： Zhifan Zhu Raghu Machiraju Bryan Fry Robert Moorhead NSF Eng. Res. Center for Computational Field Simulation P.O. Box 9627 Mississippi State University MS and Center For Air Sea Technology Mississippi State University Department of Computer Science Mississippi State University Mississippi and NSF Eng. Res. Center for Computational Field Simulation P.O. Box 9627 Mississippi State University MS Department of Electrical and Computer Engineering Mississippi State University Mississippi and NSF Eng. Res. Center for Computational Field Simulation P.O. Box 9627 Mississippi State University MS

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A simulator for real-time parallel processing architectures 28

A simulator for real-time parallel processing architectures

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28th Annual simulation Symposium, ANSS 1995

作者： Saha, Arindam Department of Electrical and Computer Engineering NSFERC for Computational Field Simulations Mississippi State University P.O. Drawer EE MS39762 United States

ISBN: (纸本)0818670916

A time-driven,jlit-based, wormhole-routed, parallel processor network simulator has been designed in C with a user-friendly Graphical User Intelface (GUI). To accommodate the unique requirements of real-time networks, the simulator is based on prioritized queues supporting various resource allocation policies. In the simulatol;special care is taken to prevent variouspos-sible kinds of overlaps (in time)and deadlock. As a consequence of real-time systems all messages are associated with priorities and every virtual channel is associatedwith the priority ofthe message it stores. The simulator contains a simple test for the convergence of the average latency, and the throughput is always monitored to verifi that it converges to the applied load. A candidate network function is accurately defined and this characterizationis detailed enough to be simulated. The simulator is used to evaluate a set of communication characteristicsthat are deemed desirable for real-time parallel processors with respect to pelformance. © 1995 IEEE

关键词： Real time systems

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A study of network routers for real-time parallel computers

A study of network routers for real-time parallel computers

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Workshop on Parallel and Distributed Real-Time Systems

作者： A. Saha R. Neogi Department of Electrical and Computer Engineering NSFERC for Computational Field Simulation Mississippi State University MS USA Motorola Austin TX USA

A candidate network function is accurately defined for real-time parallel computers. A concise, time-driven, flit-based, priority-driven, wormhole-routed, network simulator has been designed. Experimentation is performed by monitoring the latency and the throughput with variations in different network parameters. Initially the destination address, message length and message priority are generated randomly with a uniform distribution. Then, various non-uniformities are introduced to mimic realistic applications. Results are plotted and analyzed.< >

关键词： computer networks Concurrent computing Delay Routing Virtual colonoscopy Transfer functions Network topology computational modeling Real time systems System recovery

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Rapid prototyping and performance evaluation of recoded multipliers using FPGAs

Rapid prototyping and performance evaluation of recoded mult...

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IEEE Southeastcon

作者： A. Saha R. Krishnamurthy NSFERC for Computational Field Simulations and Department of Electrical and Computer Engineering Mississippi State University Karlsruhe MS Germany Department of Electrical and Computer Engineering Mississippi State University Karlsruhe MS Germany

High speed recoded parallel multipliers constitute an affordable improvement compared to the serial-parallel add-shift designs. We present in this paper, a detailed discussion of the development of these recoded multiplier algorithms and their FPGA implementations. The various issues involved in the design process are highlighted. The cost-performance comparison of the various recoded multipliers is studied and a discussion on the design methodology is also presented.< >

关键词： Prototypes field programmable gate arrays Logic arrays Design engineering Design methodology Hardware Design optimization Algorithm design and analysis Routing computational modeling

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Some design issues in multi-chip FPGA implementation of DSP algorithms

Some design issues in multi-chip FPGA implementation of DSP ...

引用

International Workshop on Rapid System Prototyping (RSP)

作者： A. Saha R. Krishnamurthy NSF/ERC for Computational Field Simulation and Department of Electrical and Computer Engineering Mississippi State University MS USA

field programmable gate arrays (FPGAs) provide an innovative and flexible platform to implement and evaluate digital signal processing (DSP) applications. A CAD design methodology which is used to implement DSP algorithms is presented. An introduction is given to the various issues involved in the multi-chip partitioning of large DSP implementations, and approaches towards efficient auto-partitioners are also discussed in detail. The design and implementation of an 8-point 1D discrete cosine transform (DCT) and its inverse (IDCT) on a processor with FPGAs is presented in this paper, as an illustrative example of a typical DSP algorithm. The processor uses 16-bit precision, is implemented on six Xilinx 4000 type FPGAs and operates at 40 MHz.< >

关键词： Algorithm design and analysis field programmable gate arrays Digital signal processing Partitioning algorithms Signal processing algorithms Discrete cosine transforms Design methodology Design automation computational modeling computer simulation

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Solution of a parallel divide-and-conquer model in the presence of overheads

Solution of a parallel divide-and-conquer model in the prese...

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IEEE Southeastcon

作者： A. Saha N. Muthukumar ERC for Computational Field Simulation MS USA Department of Electrical and Computer Engineering IO.Drawer EE Mississippi State University MS USA

The authors describe the model for a parallel divide-and-conquer algorithm incorporating both the symmetric and nonsymmetric overheads inherent in any parallel computing environment. An algorithm for computing optimal partitions is derived. This algorithm separates problem sizes into classes of problems that may use the same optimal partition size.< >

关键词： Partitioning algorithms Parallel processing Costs Concurrent computing computational modeling Optical wavelength conversion Minimax techniques Algorithm design and analysis Parallel machines Equations

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