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IEEE TRANSACTIONS ON INFORMATION THEORY 1982年第5期28卷 701-713页

作者： NEUHOFF, DL GILBERT, RK Department of Electrical and Computer Engineering University of Michigan Ann Arbor MI USA Computer Information and Control Engineering Program University of Michigan Ann Arbor MI USA

Causal source codes are defined. These include quantizers, delta modulators, differential pulse code modulators, and adaptive versions of these. Several types of causal codes are identified. For memoryless sources it is shown that the optimum performance attainable by causal codes can be achieved by memoryless codes or by time-sharing memoryless codes. This optimal performance can be evaluated straightforwardly.

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The Need for Dynamic Routing in A Network Spanning Several Time Zones

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IEEE Communications Magazine 1982年第4期20卷 13-17页

作者： Chou, W. Nilsson, A.A. Bragg, A.W. Computer Science and Electrical Engineering Computer Studies Program North Carolina State University Raleigh Department of Electrical Engineerin North Carolina State University Raleigh

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Overview of an arithmetic design system

Overview of an arithmetic design system

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DAC 1981 - the 18th Design Automation Conference

作者： Atkins, D.E. Liu, W. Ong, S. Systems Engineering Laboratory Department of Electrical and Computer Engineering Program in Computer Information and Control Engineering University of Michigan Ann ArborMI48109 United States

This paper describes an evolving Arithmetic Design System (ADS) to support the quantitative evaluation of alternate number systems with respect to a given application and realization technology. A finite number system is a tuple consisting of a symbol set (elements are called "digit-vectors"), an interpretation set, a mapping between these two sets, and a set of operators ("digit-vector algorithms") defined on the symbol set. A set of these digit vector algorithms are proposed for conducting arithmetic design and for computing time and space complexity of compositions of these algorithms. Once a transition has been made from arithmetic design to logic design, a sub-system of the ADS provides a estimate of time and space complexity with respect to a PLA-base of implementation. © Institute of electrical and Electronics Engineers Inc. All rights reserved.

关键词： Numbering systems

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Case study of a VLSI design project: A simple inner product machine

Case study of a VLSI design project: A simple inner product ...

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computer Arithmetic (ARITH)

作者： R. A. Rutenbar Y. E. Park Department of Electrical and Computer Engineering and Program in Computer. Information and Control Engineering University of Michigan Ann Arbor MI USA

We present a case study of the application of recently evolved structured VLSI design methodologies to the design and implementation of a simple VLSI quasi-serial inner product machine.

关键词： Very large scale integration Registers Timing Adders Algorithm design and analysis Logic gates IP networks

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Towards quantitative comparison of computer number systems

Towards quantitative comparison of computer number systems

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computer Arithmetic (ARITH)

作者： S. Ong D. E. Atkins Systems Engineering Laboratory Department of Electrical and Computer Engineering University of Michigan Ann Arbor MI USA Program in Computer Information and Control Engineering University of Michigan Ann Arbor MI USA

This paper describes an evolving Arithmetic Design System (ADS) to support the quantitative evaluation of alternate number systems with respect to a given application and realization technology. In computer arithmetic we are concerned with establishing a correspondence between abstract quantities (numbers) and some physical representation (symbols), and with simulating the operations on these symbols. The ADS is intended to help study the cost and performance of alternate simulations. A finite number system is a triple consisting of a symbol set (elements are called "digit-vectors"), an interpretation set, a mapping between these two sets, and a set of operators (digit-vector algorithms) defined on its symbol set. A set of these digit vector algorithms are proposed for conducting arithmetic design. A number system matrix defines the digit vector algorithm for numerous number systems and a method for computing time and space complexity of compositions of these algorithms is proposed. An example of how the system could be used to compare addition, with and without overflow detection, for three number systems is given.

关键词： Vectors Complexity theory computers Algorithm design and analysis Finite element methods Hardware Digital arithmetic

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Prevention of task overruns in real-time non-preemptive multiprogramming systems

Prevention of task overruns in real-time non-preemptive mult...

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1980 International Symposium on computer Performance Modelling, Measurement and Evaluation, PERFORMANCE 1980

作者： Kim, K.H. Naghibzadeh, Mahmoud Computer Science Program University of South Florida TampaFL33620 United States Department of Electrical Engineering University of Southern California Los AngelesCA90007 United States

ISBN: (纸本)0897910192

Real-time multiprogramming systems, in which a hardware processor is dynamically assigned to run multiple software processes each designed to control an important device (user), are considered. Each software process executes a task in response to a service request repeatedly coming from the corresponding user. Each service task is associated with a strict deadline, and thus the design problem that we are concerned with is to ensure that the service tasks requested can always be executed within the associated deadlines, i.e., no task overrun occurs. This problem was studied by several investigators for the cases where preemptive scheduling strategies are used. In contrast, very few studies have been conducted for cases of non-preemptive scheduling. In this paper we show that a non-preemptive strategy, called relative urgency non-preemptive (RUNP) strategy, is optimal in the sense that if a system runs without a task overrun under any non-preemptive strategy, it will also run without a task overrun under the RUNP strategy. Then an efficient procedure used at the design time for detecting the possibility of a task overrun in a system using the RUNP strategy is presented. The procedure is useful in designing overrun-free real-time multiprogramming systems that yield high processor utilizations. Some special types of systems using the RUNP strategy for which even simpler detection procedures are available are also discussed. Index words: Real-time multiprogramming, task overrun, non-preemptive scheduling, time critical process, relative urgency. © Proceedings of the 1980 ACM Conference on LISP and Functional programming, LFP 1980. All rights reserved.

关键词： Scheduling

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CENTML CONTROL SYSTEM TRAINING THROUGH STA TIC AND DYNAMIC SIMULATION

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Naval Engineers Journal 1980年第2期92卷 196-206页

作者： HALL, EDWIN E. MOSS, DONALD G. NORRIS, CLIFFORD S. PETERSON, HAROLD D. Mr. Edwin E. Hall received his Bachelor's degree in Electronics from Oklahoma City University. He also is a certified College-Level Instructor in the state of Florida and has done graduate work in Computer Science at the University of Florida. As the Technical Publications and Training Manager Simulation and Control Systems Department. General Electric Company Daytona Beach Fla. he currently is responsible for the costing. planning performance scheduling and timely completion of the Department's Technical Manuals and Technical Training Programs. These Training and Manual contracts cover Ship Systems Programs. Simulation Programs. and Communications Programs for the Armed Services and commercial customers. Mr. Hall has over twenty-years experience as a Technical Writer and Instructor and for the past seventeen years has been at the General Electric Company's Daytona Beach Facility. His experience ranges from teaching Basic Electronics and Radar Circuitry as a civilian instructor for the U.S. Army to writing Manuals Proposals Reports Specifications and Brochures for General Electric's product lines. Mr. Donald G. MOSS is a graduate of Kansas State University from which he received both his B.S. degree in Business Administration and his M.S. degree in Electrical Engineering. He is presently a Senior Systems Engineer for Control Systems in the Simulation and Control Systems Department at the General Electric Company's Daytona Beach Facility. He has been employed by General Electric for 23 years — the first seven as an Engineer and Program Manager on the Fire Control Systems for the Fleet Ballistics Missile Program the next six managing the design of control and checkout equipment on the APOLLO Program and the last ten years working on control equipment for the machinery plants of new Navy ships. Over the span of years at General Electric he has worked on propulsion control for the DD-963 propulsion electric plant and auxiliary control for the FFG-7: propulsion boiler burner electric auxiliary and car

Dynamic Simulation is defined as the hardware and software required to present to the student operator visual and audible cues and responses that are the same as those encountered when operating the Control Consoles aborad ship. This type of simulation is considered essential to the development of operator skills for critical tasks. Less critical tasks can be practiced using static simulation devices. This paper discusses the utilization of these types of training devices to train Navy crews. An overview of the Machinery Control Systems of the FFG 7 and AO 177 Class ships is discussed to provide an understanding of state‐of‐the‐art equipment development. The training programs for these two ship Classes are then reviewed to show how simulation devices are currently used by the Training Community, and this is followed by a brief discussion of the additional benefits that also are derived. © 1980 by the American Society of Naval Engineers, Inc.

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Time-Component Complexity of Two Approaches to Multioperand Binary Addition

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IEEE Transactions on computers 1979年第12期C-28卷 918-926页

作者： Atkins, Daniel E. Ong, Shau-Chi Program in Computer Information and Control Engineering the Systems Engineering Laboratory of the Department of Electrical and Computer Engineering University of Michigan Ann Arbor MI 48109 United States

Component and time complexity measures in terms of number of gates and gate delays, respectively, are derived for two multioperand adder structures: a tree of carry-save adders and a tree of carry-lookahead adders. The parameters of the complexity measures are operand length, number of operands, and maximum fanin to the gates. The analysis involves a constructive derivation of the complexity of carry-lookahead networks including optimization by removal of redundant paths. An alternate measure of component complexity, number of packages with a given number of pinouts, rather than number of gates, is also presented. The general conclusion of the paper is that, under the assumptions made, for a large set of design parameters, the carry-save adder structure requires both less time and fewer components than the functionally equivalent carry-lookahead adder structure. Copyright © 1979 by The Institute of electrical and Electronics Engineers, Inc.

关键词： binary addition carry-lookahead adder carry-save adder Index Terms-Adder tree multioperand addition time-component complexity

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Space-time tradeoffs for linear recursion 79

Space-time tradeoffs for linear recursion

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6th ACM SIGACT-SIGPLAN Symposium on Principles of programming Languages, POPL 1979

作者： Swamy, Sowmitri Savage, John E. Coordinated Science Laboratory Department of Electrical Engineering University of Illinois UrbanaIL61801 United States Program in Computer Science Division of Engineering Brown University ProvidenceRI02912 United States

ISBN: (纸本)9781450373579

A linear recursive procedure is one in which a procedural call can activate at most one other procedural call. When linear recursion cannot be replaced by iteration, it is usually implemented with a stack of size proportional to the depth of recursion. In this paper we analyze implementations of linear recursion which permit large reductions in storage space at the expense of a small increase in computation time. For example, if the depth of recursion is n, storage space can be reduced to √n at the cost of a constant factor increase in running time. The problem is treated by abstracting linear recursion into the pebbling of a simple graph and for this abstraction we exhibit the optimal space-time tradeoffs. © 1979 ACM.

关键词： Abstracting

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8th International Symposium on Multiple-Valued Logic, MVL 1978

作者： Atkins, D.E. Program in Computer Information and Control Engineering Systems Engineering Laboratory Department of Electrical and Computer Engineering University of Michigan Ann ArborMI48109 United States

An approach to the topic of computer arithmetic is suggested which may have a particular conceptual, pedagodical, and practical appeal to the designer of multiple-valued logic processors. computer arithmetic deals with the physical representation of finite sets of numbers and the design, analysis, and implementation of algorithms for mechanizing arithmetic operations on these sets. Finite number representation systems (FNRS) are specified by defining a set of symbols and a mapping from the elements of this symbol set to a subset of the real numbers. A formal definition of a FNRS provides a basis for a set of definitions which in turn provide the framework for the classification of a large set of number systems. Emphasis in this paper is on the following positive, fixed radix systems: unsigned, sign and magnitude, radix complement, and diminished radix complement. We offer an annotated listing of primitive digit vector algorithms for the four common number representation systems with an arbitrary, positive integer, fixed radix. These digit vector algorithms are ones which the designer of multi-valued logic arithmetic processors will need to implement to provide general arithmetic computation. © 1978 Advanced Automotive Batteries. All rights reserved.

关键词： Numbering systems

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