Magnetic resonance imaging (MRI) presents an alternative imaging method over conventional X-ray based modalities for guiding minimal invasive surgeries. However, lack of commercial MRI safe and functional intervention...
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We report Ge23Sb7S70 chalcogenide ring resonators with up to 8 × 104 quality factors operating around 3.6 µm wavelength fabricated through e-beam lithography. Their rib waveguide geometry can be engineered t...
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Bypass capacitances bridge the gap between momentary surges of power demand caused by switching transistors and the ability of power supplies to respond to these surges. Even though bypass capacitances are not explici...
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ISBN:
(纸本)9798400713965
Bypass capacitances bridge the gap between momentary surges of power demand caused by switching transistors and the ability of power supplies to respond to these surges. Even though bypass capacitances are not explicitly specified in FPGA architectural specifications, the gate capacitances of quiescent transistors in an FPGA architecture can act as symbiotic bypass capacitances. Since any additional dedicated bypass capacitances can increase the implementation area of an FPGA, it is important to measure the ability of the quiescent bypass capacitances in maintaining stable operating voltages while the FPGA is powered by voltage sources with limited power outputs. This work measures the ability of the quiescent bypass capacitances in maintaining stable supply voltages under limited power in the context of FPGA architectural investigations. We found that, for the 12-LUT logic cluster investigated in this work, to limit VDD value droop to 5% of the nominal VDD value, the power source must be able to produce 3 times of the average power consumed by the same logic cluster powered by an ideal voltage source. When the power output is further reduced, VDD value droop increases, resulting in significantly increased delay and reduced noise margin. In addition, the degree of parallel execution also has a significant effect on VDD value. In particular, at the nominal VDD value of 0.9 volts and the maximum power output of 28.1 uW, executing all 12 LUTs in parallel results in VDD value drooping to a minimum value of 0.370 volts while executing 1 LUT at a time results in VDD value drooping to a minimum of 0.690 volts, with both cases achieving similar computing time. These results suggest that FPGA architectural evaluations should take bypass capacitances and the power limit of voltage sources into consideration in order to design efficient FPGA architectures for low power applications.
Traumatic brain injuries (TBIs) are a major health risk that increases with age. Natural brain aging results in cerebral atrophy and the enlargement of the ventricular regions. The objective of this study is to invest...
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Sleep is the natural state of relaxation for human being. Sleep quality is an essential yet frequently neglected aspect of sleep in general. Sleep quality is essential because it allows the body to restore itself and ...
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This paper provides a comparative study of dynamic comparators in low-voltage successive approximation register (SAR) analog-to-digital converters (ADCs). The architecture, comparison time, and power consumption of fo...
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ISBN:
(数字)9798350387179
ISBN:
(纸本)9798350387186
This paper provides a comparative study of dynamic comparators in low-voltage successive approximation register (SAR) analog-to-digital converters (ADCs). The architecture, comparison time, and power consumption of four widely used dynamic comparators are studied first. It is followed with an investigation of kickback in these comparators. We show although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converter (DAC) of SAR ADCs arising from the different channel resistances of DAC switches and manifesting itself only when supply voltage is low gives rise to a differential clock kickback that occurs earlier than output regeneration kickback with more strength and dictates the kickback of dynamic comparators. The dependence of the clock kickback on the input of SAR ADCs in least significant bit (LSB) conversion where the input is the smallest is investigated. The offset voltage of the dynamic comparators and its dependence on supply voltage are also investigated.
Developing on-chip functional devices requires reliable fabrication methods with high resolution for miniaturization,desired components for enhanced performance,and high throughput for fast prototyping and mass ***,la...
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Developing on-chip functional devices requires reliable fabrication methods with high resolution for miniaturization,desired components for enhanced performance,and high throughput for fast prototyping and mass ***,laser-based bubble-pen lithography(BPL)has been developed to enable sub-micron linewidths,in situ synthesis of custom materials,and on-demand patterning for various functional components and *** exploits Marangoni convection induced by a laser-controlled microbubble to attract,accumulate,and immobilize particles,ions,and molecules onto different *** years have witnessed tremendous progress in theory,engineering,and application of BPL,which motivated us to write this ***,an overview of experimental demonstrations and theoretical understandings of BPL is ***,we discuss the advantages of BPL and its diverse applications in quantum dot displays,biological and chemical sensing,clinical diagnosis,nanoalloy synthesis,and *** conclude this review with our perspective on the challenges and future directions of BPL.
A gated ring oscillator time amplifier (GROTA) featuring a well-defined programmable gain, the ability to amplify a pico-second input, an unlimited range of gain, and full compatibility with technology is proposed. Th...
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ISBN:
(数字)9798350330991
ISBN:
(纸本)9798350331004
A gated ring oscillator time amplifier (GROTA) featuring a well-defined programmable gain, the ability to amplify a pico-second input, an unlimited range of gain, and full compatibility with technology is proposed. The transfer characteristics of the GROTA and a time offset tuning mechanism enabling the amplification of a pico-second input are presented. The characteristics and impact of supply noise and device noise are studied. A variable-gain time integrator consisting of the proposed GROTA and a bi-directional gated ring oscillator (BD-GRO) time integrator is developed and its silicon implementation in TSMC 120 nm 1.2 V CMOS is provided with simulation results.
In this paper, we propose a novel efficient digital twin (DT) data processing scheme to reduce service latency for multicast short video streaming. Particularly, DT is constructed to emulate and analyze user status fo...
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The ultra-dense low earth orbit (UD-LEO) satellite network is being vigorously developed due to its great potential in providing global coverage and services. For the sake of improved network performance in resource-c...
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