The advances of machine learning (ML), and artificial intelligence (AI) in general, have attracted unprecedented attention in different applications (such as image classification, video computing, natural language pro...
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ISBN:
(数字)9798350351422
ISBN:
(纸本)9798350351439
The advances of machine learning (ML), and artificial intelligence (AI) in general, have attracted unprecedented attention in different applications (such as image classification, video computing, natural language processing, etc.). Nevertheless, due to the black-box nature and concern for sustainability of ML models, especially deep neural networks (DNNs), green and interpretable learning have been extensively studied in recent years, despite suspicions on effectiveness, subjectivity of interpretability and complexity. To address some of the concerns, this paper first explores a mathematics-inspired (M-I) learning model, which is green in nature with numerous interpretable properties. It will then present several application examples in object recognition and action recognition to demonstrate that the M-I methodology promises a plausible and sustainable path for natural evolution of machine learning.
Single-lead electrocardiographic (ECG) monitoring wearables are becoming candidate technologies for long-term remote monitoring applications. Current wearable disadvantages include high power consumption from computat...
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ISBN:
(数字)9798350371499
ISBN:
(纸本)9798350371505
Single-lead electrocardiographic (ECG) monitoring wearables are becoming candidate technologies for long-term remote monitoring applications. Current wearable disadvantages include high power consumption from computational complex pre-processing leading to low battery life. A hardware (HW) architecture for dry electrode-based ECG signal processing to increase wearable longevity is proposed. The technology is based off an analog-front end (AFE) chip combined with a field programmable gated arrays (FPGA)-based optimized cubic Hermite interpolation approach for signal processing. This system is deployed on a FPGA board featuring a single-core processor. The architecture uses 0.01 W, utilizes 0.67% and 0.44% of available look-up-tables (LUTs) and flip-flops (FFs) components on FPGA and performed real-time signal processing. Signal quality indexes (SQIs) and signal to noise ratios (SNR) information are computed where the HW processed signals showed an average SNR of 16.4 dB. ECG R-peaks are visually identified, making this architecture suitable for heart rate (HR), and heart rate variability (HRV) estimations in long-term dry-electrode single-lead ECG monitoring applications.
This paper provides a comparative study of dynamic comparators in low-voltage successive approximation register (SAR) analog-to-digital converters (ADCs). The architecture, comparison time, and power consumption of fo...
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ISBN:
(数字)9798350387179
ISBN:
(纸本)9798350387186
This paper provides a comparative study of dynamic comparators in low-voltage successive approximation register (SAR) analog-to-digital converters (ADCs). The architecture, comparison time, and power consumption of four widely used dynamic comparators are studied first. It is followed with an investigation of kickback in these comparators. We show although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converter (DAC) of SAR ADCs arising from the different channel resistances of DAC switches and manifesting itself only when supply voltage is low gives rise to a differential clock kickback that occurs earlier than output regeneration kickback with more strength and dictates the kickback of dynamic comparators. The dependence of the clock kickback on the input of SAR ADCs in least significant bit (LSB) conversion where the input is the smallest is investigated. The offset voltage of the dynamic comparators and its dependence on supply voltage are also investigated.
The United Arab Emirates has a large and sophisticated street lighting infrastructure; therefore, the photometric performance of the street lighting systems must be prioritized. Locating the malfunctions in a large st...
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ISBN:
(数字)9798350362541
ISBN:
(纸本)9798350362558
The United Arab Emirates has a large and sophisticated street lighting infrastructure; therefore, the photometric performance of the street lighting systems must be prioritized. Locating the malfunctions in a large street lighting infrastructure can be time-consuming and arduous. In this paper, a low-cost street lighting performance monitoring system is designed, implemented, and tested. The proposed system comprises three main components: an illuminance sensor, a spectrometer, and a GNSS receiver. These components build a light and robust system to mount on vehicles' rooftops. Additionally, a comprehensive data analysis and inference engine is developed to determine the photometric performance of the lighting poles by identifying the number and the position of the defective luminaires, under-performing luminaires, poles obstructed by vegetation, and lighting poles that suffer from a complete power outage due to electrical faults in lighting control cabinets. Lastly, the field survey results are demonstrated in reports and interactive online visualization using Google Maps, in which the obtained information can be converted into performance metrics and indexes overlayed on urban maps.
In this paper, we propose a novel efficient digital twin (DT) data processing scheme to reduce service latency for multicast short video streaming. Particularly, DT is constructed to emulate and analyze user status fo...
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Traumatic brain injuries (TBIs) are a major health risk that increases with age. Natural brain aging results in cerebral atrophy and the enlargement of the ventricular regions. The objective of this study is to invest...
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This paper presents area-efficient edge-triggered bi-directional gated delay line (BDGDL) thermometer up-down counters. The principle, operation, and design considerations of the proposed counters are detailed. An 8b ...
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ISBN:
(数字)9798350387179
ISBN:
(纸本)9798350387186
This paper presents area-efficient edge-triggered bi-directional gated delay line (BDGDL) thermometer up-down counters. The principle, operation, and design considerations of the proposed counters are detailed. An 8b positive edge-triggered DBGDL up-down counter is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.8 V. Simulation results show the counter performs both up-counting and down-counting correctly at FF/-20°C, TT/27°C, and SS/60°C. The number of transistors per stage of the proposed counter is 13 while that of its MUX/DFF counterpart is 40, a reduction of 67.5%.
We report Ge23Sb7S70 chalcogenide ring resonators with up to 8 × 104 quality factors operating around 3.6 µm wavelength fabricated through e-beam lithography. Their rib waveguide geometry can be engineered t...
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This paper proposes an alternative detection frame-work for multiple sclerosis (MS) and idiopathic acute transverse myelitis (ATM) within the 6G-enabled Internet of Medical Things (IoMT) environment. The developed fra...
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