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Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip

IEEE Access 2025年 13卷 37493-37500页

作者： Lee, Seung-Han Park, Jin Hwan Lee, Young-Woo Inha University Department of Electrical and Computer Engineering Incheon22212 Korea Republic of Inha University Program in Semiconductor Convergence Incheon22212 Korea Republic of Teradyne Inc. Semiconductor Test Division MA North Reading01864 United States

semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conducted using Automatic Test Equipment (ATE) along with test infrastructures such as the Prober Interface Board (PIB), signal tower, and probe card. In this paper, we present the mechanical and electrical details of a wafer-level test infrastructure designed for higher parallel testing of system-on-chips (SoCs). In previous test infrastructures, a high site count was constrained by the available probe pins on the signal tower for wafer testing. However, the proposed signal tower addresses this bottleneck by utilizing a combination of 620 pin and 731 pin modules. This allows more probe pins to transmit signals from the ATE instrument, enabling multi-site testing. The number of available probe pins increased by 68.96% compared to the state-of-the-art infrastructure, without compromising the application area. The experimental results demonstrate that our proposed test infrastructure is suitable for mass production at the wafer-level, considering factors such as deflection, total compression forces, and electrical specifications. © 2025 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://***/licenses/by/4.0/

关键词： System-on-chip

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A Pulse Width Modulation-Based Spike Generator to Eliminate Timing Errors in Spiking Neural Networks

A Pulse Width Modulation-Based Spike Generator to Eliminate ...

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2025 International Conference on Electronics, Information, and Communication, ICEIC 2025

作者： Jo, Jungkook Sim, Keonhee Sim, Sangwoong Jun, Jaehoon Inha University Dept. of electrical and computer engineering and program in semiconductor convergence Incheon Korea Republic of Inha University Dept. of electrical engineering Incheon Korea Republic of

ISBN: (纸本)9798331510756

This paper proposes a novel spike generator for processing in memory (PIM) technology. Most of the electronics today utilize a von Neumann architecture. The von Neumann architecture suffers from the separation of memory and processor. This architecture delays data transfer between memory and processor. To overcome the issues, we utilize the spiking neural network (SNN) that combines memory and processor. SNN can be classified into voltage-based, current-based, and time-based architectures, each with its own pros and cons. Time-based SNN suffers from timing issues. To address the timing sensitivity of time-based neuron SNN, this paper proposes a PWM-based SNN. The PWM-based SNN utilizes pulse width-based logic to overcome timing sensitivity. © 2025 IEEE.

关键词： Pulse width modulation

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Redefining PIM Architecture with Compact and Power-Efficient Microscaling

Redefining PIM Architecture with Compact and Power-Efficient...

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2025 International Conference on Electronics, Information, and Communication, ICEIC 2025

作者： Jang, Yoonho Cho, Hyeongjun Hong, Seokin Sungkyunkwan University Department of Electrical and Computer Engineering Suwon Korea Republic of Sungkyunkwan University Department of Semiconductor Convergence Engineering Suwon Korea Republic of

ISBN: (纸本)9798331510756

With advances in neural network technology, Processing-In-Memory (PIM) has emerged as a solution to per-formance bottlenecks between processors and memory. Among various PIM design techniques, integrating processing units within memory banks has demonstrated high performance in accelerating neural network models. However, prior architectures based on this approach have required sacrificing a large portion of the cell array to accommodate complex floating-point pro-cessing units. In this paper, we propose a new architecture that incorporates a unique quantization technique called microscaling. This technique efficiently converts high-precision data to integer types with minimal accuracy loss during model inference. By adopting microscaling, we reduce the processing unit overhead by replacing floating-point units with integer-based ones. As a result, our approach achieves a 50 % reduction in area while maintaining equivalent performance and reduces energy consumption to approximately 70 % of that in prior architectures. © 2025 IEEE.

关键词： Memory architecture

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Redefining PIM Architecture with Compact and Power-Efficient Microscaling

Redefining PIM Architecture with Compact and Power-Efficient...

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International Conference on Electronics, Information and Communications (ICEIC)

作者： Yoonho Jang Hyeongjun Cho Seokin Hong Department of Electrical and Computer Engineering Sungkyunkwan University Suwon Korea Department of Semiconductor Convergence Engineering Sungkyunkwan University Suwon Korea

ISBN: (数字)9798331510756

ISBN: (纸本)9798331510763

关键词： Energy consumption Quantization (signal) Accuracy program processors Microprocessors Neural networks computer architecture Hardware Data models Arrays

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A Pulse Width Modulation-Based Spike Generator to Eliminate Timing Errors in Spiking Neural Networks

A Pulse Width Modulation-Based Spike Generator to Eliminate ...

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International Conference on Electronics, Information and Communications (ICEIC)

作者： Jungkook Jo Keonhee Sim Sangwoong Sim Jaehoon Jun dept. of electrical and computer engineering and program in semiconductor convergence Inha University Incheon Republic of Korea dept. of electrical engineering Inha University Incheon Republic of Korea

ISBN: (数字)9798331510756

ISBN: (纸本)9798331510763

关键词： Sensitivity Image edge detection Neurons Spiking neural networks Data transfer Generators Delays Logic Next generation networking Clocks

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FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration

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IEEE Transactions on computer-Aided Design of Integrated Circuits and Systems 2025年

作者： Nguyen, Kihwan Kim Xuan Truong Jeon, Dongsuk Lee, Hyuk-Jae Korea Republic of program Department of Electrical Engineering Seoul08826 Korea Republic of Inter-University Semiconductor Research Center Seoul National University Graduate School of Convergence Science and Technology Research Institute for Convergence Science Seoul08826 Korea Republic of Department of Electrical and Computer Engineering Seoul08826 Korea Republic of

Video super-resolution (VSR) is widely used in various high-definition applications, such as HDTVs and smartphones, requiring a dedicated upscaling technique for realtime full-HD generation. To reduce on-chip buffers for largesize output feature maps, a streaming VSR accelerator may employ an output stationary dataflow, leading to a large energy consumption caused by frequent filter switching. To mitigate this, we introduce a new filter-dedicated multiplier design for realtime VSR acceleration. We replace costly multipliers with adders, shifters, and multiplexers (MUXes), referred to as unified multiple constant multiplications (UMCM). The conventional UMCM, however, may incur considerable area/power overhead due to the unified topology constraint among different filter sets. To address this problem, we propose a new approximated MCM (AMCM) problem to relax the constraint and an approximate compatible graph synthesis (A-CGS) framework to efficiently solve AMCM by jointly searching for approximated filters and constructing a unified graph. Additionally, we suggest a lightweight finetuning method by freezing approximated filters and only finetuning biases, which can recover the original model’s accuracy within a few epochs. Experimental results with synthetic data demonstrate that AMCM reduces the area by up to 49.8%, 44.8%, and 40.3% when considering constant sets of 2, 4, and 8, respectively. Our designs with SR application achieve up to a 73.3% reduction in energy consumption. Experiments with the Set5 and Set14 datasets show that our model with bias correction achieves similar restoration performance compared to the eightbit models. © 1982-2012 IEEE.

关键词： Acceleration

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Zebra: Leveraging Diagonal Attention Pattern for Vision Transformer Accelerator

Zebra: Leveraging Diagonal Attention Pattern for Vision Tran...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Sukhyun Han Seongwook Kim Gwangeun Byeon Jihun Yoon Seokin Hong Department of Semiconductor Convergence Engineering Sungkyunkwan University Suwon Republic of Korea Department of Electrical and Computer Engineering Sungkyunkwan University Suwon Republic of Korea

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Vision Transformers (ViTs) have achieved remarkable performance in computer vision, but their computational complexity and challenges in optimizing memory bandwidth limit hardware acceleration. A major bottleneck lies in the self-attention mechanism, which leads to excessive data movement and unnecessary computations despite high input sparsity and low computational demands. To address this challenge, existing transformer accelerators have leveraged sparsity in attention maps. However, their performance gains are limited due to low hardware utilization caused by the irregular distribution of nonzero values in the sparse attention maps. Self-attention often exhibits strong diagonal patterns in the attention map, as the diagonal elements tend to have higher values than others. To exploit this, we introduce Zebra, a hardware accelerator framework optimized for diagonal attention patterns. A core component of Zebra is the Striped Diagonal (SD) pruning technique, which prunes the attention map by preserving only the diagonal elements at runtime. This reduces computational load without requiring offline pre-computation or causing significant accuracy loss. Zebra features a reconfigurable accelerator architecture that supports optimized matrix multiplication method, called Striped Diagonal Matrix Multiplication (SDMM), which computes only the diagonal elements of matrices. With this novel method, Zebra addresses low hardware utilization, a key barrier to leveraging the diagonal patterns. Experimental results demonstrate that Zebra achieves a 57 × speedup over a CPU and 1.7 × over the state-of-the-art ViT accelerator with similar inference accuracy.

关键词： computer vision Accuracy Runtime Accelerator architectures Europe Performance gain Transformers Sparse matrices Computational complexity Hardware acceleration

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Damage-Free Neutral Beam Etching for Gate Recess in E-Mode AlGaN/GaN HEMTs

IEEE Electron Device Letters

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IEEE Electron Device Letters 2025年第5期46卷 705-708页

作者： Chen, Yi-Ho Chu, Fu-Chuan Aslam, Muhammad Lee, Yao-Jen Li, Yiming Samukawa, Seiji National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Graduate Degree Program of College of Electrical and Computer Engineering Hsinchu300093 Taiwan National Chung-Shan Institute of Science and Technology Solid State Devices Section Electronic System Research Division Taoyuan325 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

Recess gate etching is a critical technique for achieving enhancement-mode (E-mode) AlGaN/GaN high-electron mobility transistors (HEMTs) because the interface is susceptible to the etching damage. This study fabricates recess gates using the neutral beam etching (NBE) technique. By adjusting the aperture thickness in the NBE apparatus, we simulate both NB-mode and plasma-mode etching. The electrical characteristics of E-mode HEMTs fabricated using these two modes are analyzed and compared through DC, noise, and pulsed IV measurements. The results demonstrate that NB-recessed HEMTs exhibit superior performance. © 1980-2012 IEEE.

关键词： Aluminum gallium nitride

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Multiplexing B5G/6G Services Over Aerial VLC Networks: A Comprehensive Radio Resource Management Framework

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IEEE Internet of Things Journal 2025年第9期12卷 11600-11621页

作者： Zarini, Hosein Gholipoor, Narges Mili, Mohammad Robat Rasti, Mehdi Movaghar, Ali Choi, Jinho Chae, Chan-Byoung Sharif University of Technology Department of Computer Engineering Tehran11365-8639 Iran University of Oulu Center for Wireless Communications Oulu90570 Finland Pasargad Institute for Advanced Innovative Solutions Tehran1111111 Iran The University of Adelaide School of Electrical and Mechanical Engineering North Terrace AdelaideSA5005 Australia Yonsei University School of Integrated Technology BK21 Graduate Program in Intelligent Semiconductor Technology Seoul03722 Korea Republic of

Downlink transmission of a nonorthogonal visible light communication (VLC) system, empowered by autonomous aerial vehicles (AAVs), is studied for coexisting enhanced mobile broadband (eMBB), ultrareliable low-latency communication (URLLC), and massive machine-type communication (mMTC) services. A joint resource allocation problem involving user association, transmit power, and flight trajectory of AAVs is formulated, with the goal of characterizing a multiobjective tradeoff as a weighted sum of the power consumption of each AAV and the perceived Quality of Experience (QoE) of its associated eMBB users, while ensuring the service-specific requirements for eMBB, mMTC, and URLLC are met. Assuming the imperfection of channel state information (CSI), we invoke a generalized Benders decomposition (GBD) methodology, leveraging tools from convex optimization and multiagent deep reinforcement learning to address this problem. We further analytically derive the upper and lower bounds on the reward function for each AAV as a learning agent. Extensive simulations confirm that our proposed method outperforms the single-agent counterpart in the literature, with up to a 22% reduction in power consumption and a 13% gain in perceived QoE. Additionally, compared to the globally optimal brute-force method for AAV-user association, our proposed method experiences only a trivial performance loss in a small-scale scenario. © 2014 IEEE.

关键词： Convex optimization

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A Low Power Digitizer Array with Adaptive Split Current Source for 3-D-Stacked 100 MP High Dynamic Range Imager

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IEEE Sensors Journal 2025年

作者： Lee, Youngwoo Kim, Seyeon Kim, Jinha Kim, Suhwan Jun, Jaehoon Seoul08826 Korea Republic of Samsung Electronics Hwaseong18448 Korea Republic of Inha University Department of Electrical and Computer Engineering Program in Semiconductor Convergence Incheon22212 Korea Republic of Seoul National University Department of Electrical and Computer Engineering Seoul08826 Korea Republic of Gwanak Analog Company Ltd Seoul08826 Korea Republic of

The increasing demand for high dynamic range (HDR), power efficiency, and high resolution has driven the adoption of single-exposure dual conversion gain (DCG) techniques. This paper proposes an adaptive split current source to optimize power consumption in single-exposure DCG readouts. By splitting the comparator bias current, the power consumption of the digitizer array can be adaptively optimized based on the conversion gain (CG) of pixel in single-exposure DCG operation. Additional power-saving features including decision-feedback and auto-zeroing (AZ) power-down techniques are also implemented to further improve power efficiency. The proposed digitizer chip was fabricated in a 28 nm CMOS process, achieving a power consumption reduction of 44.5% in comparator. The integral nonlinearity (INL) was measured as +2.67/–2.34 LSB in high conversion gain (HCG) and +2.95/–1.92 LSB in low conversion gain (LCG). The input-referred random noise (RN) values of 2.17 LSB (HCG) and 2.41 LSB (LCG) were measured at an analog gain of 16, corresponding to 93 μVrms and 103 μVrms, respectively. The prototype chip shows a highly competitive figure of merit (FoM) of 2.41 mV∙pJ/pixel/frame. © 2001-2012 IEEE.

关键词： CMOS integrated circuits

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