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Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip

IEEE Access 2025年 13卷 37493-37500页

作者： Lee, Seung-Han Park, Jin Hwan Lee, Young-Woo Inha University Department of Electrical and Computer Engineering Incheon22212 Korea Republic of Inha University Program in Semiconductor Convergence Incheon22212 Korea Republic of Teradyne Inc. Semiconductor Test Division MA North Reading01864 United States

semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conducted using Automatic Test Equipment (ATE) along with test infrastructures such as the Prober Interface Board (PIB), signal tower, and probe card. In this paper, we present the mechanical and electrical details of a wafer-level test infrastructure designed for higher parallel testing of system-on-chips (SoCs). In previous test infrastructures, a high site count was constrained by the available probe pins on the signal tower for wafer testing. However, the proposed signal tower addresses this bottleneck by utilizing a combination of 620 pin and 731 pin modules. This allows more probe pins to transmit signals from the ATE instrument, enabling multi-site testing. The number of available probe pins increased by 68.96% compared to the state-of-the-art infrastructure, without compromising the application area. The experimental results demonstrate that our proposed test infrastructure is suitable for mass production at the wafer-level, considering factors such as deflection, total compression forces, and electrical specifications. © 2025 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://***/licenses/by/4.0/

关键词： System-on-chip

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A Pulse Width Modulation-Based Spike Generator to Eliminate Timing Errors in Spiking Neural Networks

A Pulse Width Modulation-Based Spike Generator to Eliminate ...

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2025 International Conference on Electronics, Information, and Communication, ICEIC 2025

作者： Jo, Jungkook Sim, Keonhee Sim, Sangwoong Jun, Jaehoon Inha University Dept. of electrical and computer engineering and program in semiconductor convergence Incheon Korea Republic of Inha University Dept. of electrical engineering Incheon Korea Republic of

ISBN: (纸本)9798331510756

This paper proposes a novel spike generator for processing in memory (PIM) technology. Most of the electronics today utilize a von Neumann architecture. The von Neumann architecture suffers from the separation of memory and processor. This architecture delays data transfer between memory and processor. To overcome the issues, we utilize the spiking neural network (SNN) that combines memory and processor. SNN can be classified into voltage-based, current-based, and time-based architectures, each with its own pros and cons. Time-based SNN suffers from timing issues. To address the timing sensitivity of time-based neuron SNN, this paper proposes a PWM-based SNN. The PWM-based SNN utilizes pulse width-based logic to overcome timing sensitivity. © 2025 IEEE.

关键词： Pulse width modulation

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Redefining PIM Architecture with Compact and Power-Efficient Microscaling

Redefining PIM Architecture with Compact and Power-Efficient...

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2025 International Conference on Electronics, Information, and Communication, ICEIC 2025

作者： Jang, Yoonho Cho, Hyeongjun Hong, Seokin Sungkyunkwan University Department of Electrical and Computer Engineering Suwon Korea Republic of Sungkyunkwan University Department of Semiconductor Convergence Engineering Suwon Korea Republic of

ISBN: (纸本)9798331510756

With advances in neural network technology, Processing-In-Memory (PIM) has emerged as a solution to per-formance bottlenecks between processors and memory. Among various PIM design techniques, integrating processing units within memory banks has demonstrated high performance in accelerating neural network models. However, prior architectures based on this approach have required sacrificing a large portion of the cell array to accommodate complex floating-point pro-cessing units. In this paper, we propose a new architecture that incorporates a unique quantization technique called microscaling. This technique efficiently converts high-precision data to integer types with minimal accuracy loss during model inference. By adopting microscaling, we reduce the processing unit overhead by replacing floating-point units with integer-based ones. As a result, our approach achieves a 50 % reduction in area while maintaining equivalent performance and reduces energy consumption to approximately 70 % of that in prior architectures. © 2025 IEEE.

关键词： Memory architecture

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Multi-Agent Deep Reinforcement Learning Based Handover Strategy for LEO Satellite Networks

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IEEE Communications Letters 2025年第5期29卷 1117-1121页

作者： Lee, Chungnyeong Bang, Inkyu Kim, Taehoon Lee, Howon Jung, Bang Chul Chae, Seong Ho Tech University of Korea Department of IT Semiconductor Convergence Engineering Siheung15073 Korea Republic of Hanbat National University Daejeon34158 Korea Republic of Ajou University Department of Electrical and Computer Engineering Suwon16499 Korea Republic of Tech University of Korea Department of Electronics Engineering Siheung15073 Korea Republic of

The high rotation speeds and mega-constellations of low earth orbit satellites (LEO SATs) cause the inter-satellite frequent handovers (HOs) problem which can lead to substantial performance degradation. This paper proposes a novel distributed multi-agent deep Q-network based SAT HO strategy for the LEO SAT networks to simultaneously minimize the number of HOs and maximize the throughputs and the visible times of UEs while satisfying the quality-of-service (QoS) constraints of all UEs. The proposed HO scheme allows UEs to independently and simultaneously perform the HO decision makings based on their own local information, which enables to immediately adapt to the dynamic changes of the LEO SAT network environments. The numerical results demonstrated that our proposed HO strategy achieves the lowest average HO rate and the highest achievable throughputs compared to other conventional HO strategies, while ensuring a higher QoS guarantee time ratio. © 1997-2012 IEEE.

关键词： Quality of service

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Redefining PIM Architecture with Compact and Power-Efficient Microscaling

Redefining PIM Architecture with Compact and Power-Efficient...

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International Conference on Electronics, Information and Communications (ICEIC)

作者： Yoonho Jang Hyeongjun Cho Seokin Hong Department of Electrical and Computer Engineering Sungkyunkwan University Suwon Korea Department of Semiconductor Convergence Engineering Sungkyunkwan University Suwon Korea

ISBN: (数字)9798331510756

ISBN: (纸本)9798331510763

关键词： Energy consumption Quantization (signal) Accuracy program processors Microprocessors Neural networks computer architecture Hardware Data models Arrays

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A Pulse Width Modulation-Based Spike Generator to Eliminate Timing Errors in Spiking Neural Networks

A Pulse Width Modulation-Based Spike Generator to Eliminate ...

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International Conference on Electronics, Information and Communications (ICEIC)

作者： Jungkook Jo Keonhee Sim Sangwoong Sim Jaehoon Jun dept. of electrical and computer engineering and program in semiconductor convergence Inha University Incheon Republic of Korea dept. of electrical engineering Inha University Incheon Republic of Korea

ISBN: (数字)9798331510756

ISBN: (纸本)9798331510763

关键词： Sensitivity Image edge detection Neurons Spiking neural networks Data transfer Generators Delays Logic Next generation networking Clocks

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FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration

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IEEE Transactions on computer-Aided Design of Integrated Circuits and Systems 2025年

作者： Nguyen, Kihwan Kim Xuan Truong Jeon, Dongsuk Lee, Hyuk-Jae Korea Republic of program Department of Electrical Engineering Seoul08826 Korea Republic of Inter-University Semiconductor Research Center Seoul National University Graduate School of Convergence Science and Technology Research Institute for Convergence Science Seoul08826 Korea Republic of Department of Electrical and Computer Engineering Seoul08826 Korea Republic of

Video super-resolution (VSR) is widely used in various high-definition applications, such as HDTVs and smartphones, requiring a dedicated upscaling technique for realtime full-HD generation. To reduce on-chip buffers for largesize output feature maps, a streaming VSR accelerator may employ an output stationary dataflow, leading to a large energy consumption caused by frequent filter switching. To mitigate this, we introduce a new filter-dedicated multiplier design for realtime VSR acceleration. We replace costly multipliers with adders, shifters, and multiplexers (MUXes), referred to as unified multiple constant multiplications (UMCM). The conventional UMCM, however, may incur considerable area/power overhead due to the unified topology constraint among different filter sets. To address this problem, we propose a new approximated MCM (AMCM) problem to relax the constraint and an approximate compatible graph synthesis (A-CGS) framework to efficiently solve AMCM by jointly searching for approximated filters and constructing a unified graph. Additionally, we suggest a lightweight finetuning method by freezing approximated filters and only finetuning biases, which can recover the original model’s accuracy within a few epochs. Experimental results with synthetic data demonstrate that AMCM reduces the area by up to 49.8%, 44.8%, and 40.3% when considering constant sets of 2, 4, and 8, respectively. Our designs with SR application achieve up to a 73.3% reduction in energy consumption. Experiments with the Set5 and Set14 datasets show that our model with bias correction achieves similar restoration performance compared to the eightbit models. © 1982-2012 IEEE.

关键词： Acceleration

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Damage-Free Neutral Beam Etching for Gate Recess in E-Mode AlGaN/GaN HEMTs

IEEE Electron Device Letters

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IEEE Electron Device Letters 2025年第5期46卷 705-708页

作者： Chen, Yi-Ho Chu, Fu-Chuan Aslam, Muhammad Lee, Yao-Jen Li, Yiming Samukawa, Seiji National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Graduate Degree Program of College of Electrical and Computer Engineering Hsinchu300093 Taiwan National Chung-Shan Institute of Science and Technology Solid State Devices Section Electronic System Research Division Taoyuan325 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

Recess gate etching is a critical technique for achieving enhancement-mode (E-mode) AlGaN/GaN high-electron mobility transistors (HEMTs) because the interface is susceptible to the etching damage. This study fabricates recess gates using the neutral beam etching (NBE) technique. By adjusting the aperture thickness in the NBE apparatus, we simulate both NB-mode and plasma-mode etching. The electrical characteristics of E-mode HEMTs fabricated using these two modes are analyzed and compared through DC, noise, and pulsed IV measurements. The results demonstrate that NB-recessed HEMTs exhibit superior performance. © 1980-2012 IEEE.

关键词： Aluminum gallium nitride

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Multiplexing B5G/6G Services Over Aerial VLC Networks: A Comprehensive Radio Resource Management Framework

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IEEE Internet of Things Journal 2025年第9期12卷 11600-11621页

作者： Zarini, Hosein Gholipoor, Narges Mili, Mohammad Robat Rasti, Mehdi Movaghar, Ali Choi, Jinho Chae, Chan-Byoung Sharif University of Technology Department of Computer Engineering Tehran11365-8639 Iran University of Oulu Center for Wireless Communications Oulu90570 Finland Pasargad Institute for Advanced Innovative Solutions Tehran1111111 Iran The University of Adelaide School of Electrical and Mechanical Engineering North Terrace AdelaideSA5005 Australia Yonsei University School of Integrated Technology BK21 Graduate Program in Intelligent Semiconductor Technology Seoul03722 Korea Republic of

Downlink transmission of a nonorthogonal visible light communication (VLC) system, empowered by autonomous aerial vehicles (AAVs), is studied for coexisting enhanced mobile broadband (eMBB), ultrareliable low-latency communication (URLLC), and massive machine-type communication (mMTC) services. A joint resource allocation problem involving user association, transmit power, and flight trajectory of AAVs is formulated, with the goal of characterizing a multiobjective tradeoff as a weighted sum of the power consumption of each AAV and the perceived Quality of Experience (QoE) of its associated eMBB users, while ensuring the service-specific requirements for eMBB, mMTC, and URLLC are met. Assuming the imperfection of channel state information (CSI), we invoke a generalized Benders decomposition (GBD) methodology, leveraging tools from convex optimization and multiagent deep reinforcement learning to address this problem. We further analytically derive the upper and lower bounds on the reward function for each AAV as a learning agent. Extensive simulations confirm that our proposed method outperforms the single-agent counterpart in the literature, with up to a 22% reduction in power consumption and a 13% gain in perceived QoE. Additionally, compared to the globally optimal brute-force method for AAV-user association, our proposed method experiences only a trivial performance loss in a small-scale scenario. © 2014 IEEE.

关键词： Convex optimization

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Corrections to “Comprehensive Analysis of Design and Performance Evaluation Methodologies for a High-Resolution Read-Out IC With Ultralow 1/ f Corner for DC Measurement Applications”

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IEEE Transactions on Instrumentation and Measurement 2025年 74卷

作者： Junho Kang Woosol Han Suhwan Kim Jaehoon Jun Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center (ISRC) Seoul National University Seoul South Korea Department of Electrical and Computer Engineering and Program in Semiconductor Convergence Inha University Incheon South Korea Department of Electrical and Computer Engineering Seoul National University Seoul South Korea Gwanak Analog Company Ltd. Seoul South Korea Department of Electrical and Computer Engineering and the Program in Semiconductor Convergence Inha University Incheon South Korea

Presents corrections to the paper, (Corrections to “Comprehensive Analysis of Design and Performance Evaluation Methodologies for a High-Resolution Read-Out IC With Ultralow 1/ f Corner for DC Measurement Application... 详细信息

关键词： Performance evaluation

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