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Multi-Scale Analysis Combined Operando Elemental/Spectroscopic Measurement Techniques in Oxide-Type All-Solid-State Na Batteries

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Energy & Environmental Materials 2025年第2期8卷 38-47页

作者： Koji Hiraoka Kazuo Yamamoto Takeshi Kobayashi Tetsuo Sakamoto Shiro Seki Graduate School of Engineering Applied Chemistry and Chemical Engineering Program Kogakuin University Nanostructures Research Laboratory Japan Fine Ceramics Center Energy Transformation Research Laboratory Central Research Institute of Electric Power Industry Graduate School of Engineering Electrical Engineering and Electronics Program Kogakuin University

Understanding the charge/discharge mechanism of batteries plays an important role in the development of high-performance systems,but extremely complicated reactions are *** these complex phenomena are also bottlenecks for the establishment of all-sol id-state batteries(ASSB),we conducted multi-scale analysis using combined multi-measurement techniques,to directly observe charge/discharge reactions at hierarchical scales for the oxide-type ASSB using Na as the carrier *** particular,all of measurement techniques are applied to cross-section ASSB in the same cell,to complementarily evaluate the elemental distributions and structural *** Operando scanning electron microscopy-energy-dispersive X-ray spectroscopy,the Na concentration in the electrode layers changes on the micrometer scale under charge/discharge reactions in the first ***,Operando Raman spectroscopy reveal changes in the bonding states at the atomic scale in the active material,including changes in reversible structural *** cycling the ASSB,the elemental distributions are clearly observed along with the particle shapes and can reveal the Na migration mechanism at the nanometer scale,by time-of-flight secondary ion mass ***,this study can provide a fundamental and comprehensive understanding of the charge/discharge mechanism by observing reaction processes at multiple scales.

关键词： Operando oxide-type all-solid-state battery Raman SEM-EDS sodium battery TOF-SIMS

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An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration

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IEEE Journal of Solid-State Circuits 2024年第11期59卷 3705-3715页

作者： Lin, Chun-Yu Chen, Wei-Han Hung, Yu-Ting Wang, Tun-Ju Lin, Tsung-Hsien Graduate Institute of Electronics Engineering National Taiwan University Department of Electrical Engineering Taipei10617 Taiwan

This article presents an open-loop fractional output divider (FOD) that employs a replica-digital-to-time converter (DTC)-free background calibration. To support fractional division operation, the divider is modulated by a Delta-Sigma modulator (DSM). A DTC that follows the divider is incorporated to compensate for the modulation noise and generate a low-deterministic-jitter output. In this work, a background DTC gain calibration is proposed to realize a high-performance FOD. This calibration features a replica-DTC-free technique to reduce chip area and power consumption. Furthermore, a two-step division architecture is adopted to relax the tradeoffs among calibration settling time, frequency resolution, and circuit design non-idealities. Fabricated in a 90-nm CMOS process, the proposed FOD supports an output frequency range of 0.625 to 200 MHz. This FOD achieves 300 fsrms integrated jitter and -65 dBc spur at 192-MHz output frequency. Operated from a 1-V supply voltage, the proposed FOD consumes 1.5 mA and the core area is only 0.008 mm2. © 1966-2012 IEEE.

关键词： Phase locked loops

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A 2.4-GHz CMOS Efficiency-Enhanced Rectifier With a Differential-Feed Patch Antenna

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IEEE Microwave and Wireless Technology Letters 2024年第2期34卷 229-232页

作者： Huang, Zhi-Yong Chen, Yi-Jan Emery Graduate Institute of Electronics Engineering the Graduate Institute of Communication Engineering the Department of Electrical Engineering National Taiwan University Taipei10617 Taiwan

This letter presents the codesign of a 2.4-GHz CMOS rectifier and an antenna for efficiency enhancement at low input power. The RF differential-driven rectifier architecture is used to lower the driving voltage required to turn on the transistors. The high-resistance feedback path with an offset voltage is added to the rectifier circuit to reduce the reverse leakage current for efficiency enhancement. The rectifier is connected directly to the differential-feed antenna to eliminate the need and loss of a balun. The measured power conversion efficiency (PCE) of the rectifier achieves 63% at the input power of −8 dBm. © 2024 Institute of electrical and electronics Engineers Inc.. All rights reserved.

关键词： Wireless sensor networks

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Analytical Modeling of the Temporal Response of the Transient Displacement Currents in MIS Tunnel Diodes Under Low-Voltage Operation

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IEEE Transactions on Electron Devices 2024年第2期71卷 1166-1172页

作者： Huang, Sung-Wei Hwu, Jenn-Gwo Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan National Taiwan University Graduate Institute of Electronics Engineering Department of Electrical Engineering Taipei10617 Taiwan

In this work, the temporal response of the transient displacement currents in a metal-insulator-semiconductor (MIS) tunnel diode with a 3-nm oxide layer under low-voltage operation ( leq 1 V) was analyzed by analytical modeling. The magnitude of the gate transient currents saturated as the write voltage became more positive. When the write voltage was much higher than the saturation write voltage, the transient current decayed inversely with time for the transient time from 200 ns to 1 ms. An analytical model was proposed to comprehend the 1/ {t}-decaying transient current behavior when the electron diffusion current dominated the substrate current, and the modeling results were consistent with the simulation results. By also considering the recombination current, gate transient currents for write voltages ranging from 0.1 to 1 V could be well modeled. The arbitrary time constant in the model could be determined by calibration with simulation data or by totally theoretical calculation. Without any input from the simulation results, the model predicted a saturation write voltage that deviated by only about 0.01 V from the actual value. © 1963-2012 IEEE.

关键词： Substrates

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A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique

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IEEE Journal of Solid-State Circuits 2024年第7期59卷 2199-2208页

作者： Chang, Hao-Hsuan Chen, Ci-Ren Lee, Tai-Cheng Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan National Taiwan University Department of Electrical Engineering Graduate Institute of Electronics Engineering Taipei10617 Taiwan

This work proposes a hybrid two-stage analog-to-digital converter (ADC) consisting of a coarse 3.3-V successive-approximation register (SAR) ADC and a fine 1.8-V comparator-based (CB) incremental Δ Σ modulator (ISDM) ADC. The coarse ADC boosts the maximum input amplitude to improve signal-to-noise and distortion ratio (SNDR), and the fine ISDM ADC adopts an asynchronous operation and a time-domain noise-slicing (TDNS) technique to improve power efficiency and conversion speed. Using the unequal data weighting of ISDM and the noise-slope relationship of the CB amplifier, the TDNS technique reconstructs the noise and power weighting of each cycle to optimize the figure of merit (FoM). Furthermore, the noise of the CB amplifier is suppressed by the noise-shaping (NS) technique. The ADC operates at a 370-kHz frequency and achieves 94.5/89.3-dB dynamic range (DR)/SNDR in a 185-kHz bandwidth (BW). It achieves a Schreier FoM of 174.88 dB and consumes 511 μ W. © 1966-2012 IEEE.

关键词： Comparators (optical)

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Measuring Public Wi-Fi Security Awareness via Captive Portal Connections Using a Microcontroller

Measuring Public Wi-Fi Security Awareness via Captive Portal...

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2024 Workshop on Communication Networks and Power Systems, WCNPS 2024

作者： Mariano, Hyago Santana Cafe, Daniel Chaves Professional Graduate Program in Electrical Engineering-PPEE Department of Electrical Engineering Brazil

ISBN: (纸本)9798331507152

This article proposes the implementation of a captive portal system on a microcontroller to assess users' maturity regarding the safe use of public Wi-Fi networks. The use of public Wi-Fi networks has become increasingly common in places like cafes, airports, shopping centers, and hotels. However, many users are unaware of the risks associated with using these unsecured networks, such as personal information theft, privacy invasion, and cyberattacks. This study aims to utilize a microcontroller to generate a signal mimicking a known public network, where, upon user login, an educational authentication portal will be displayed. This portal will not only provide information about security risks but also evaluate the users' maturity level in adopting safe practices on public Wi-Fi networks, offering guidelines on how to protect their data and devices. © 2024 IEEE.

关键词： Wi-Fi

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A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2024年第7期32卷 1263-1272页

作者： Lan, Yi-Hao Liu, Shen-Iuan National Taiwan University Graduate Institute of Electronics Engineering The Department of Electrical Engineering Taipei10617 Taiwan

A 36-Gb/s 2× half-baud-rate (THBR) adaptive receiver (RX) is presented. The pattern-based adaptation method for adjusting the frequency response of a continuous-time linear equalizer (CTLE) is proposed. In addition, the reference voltage of the comparators is adapted to enhance the timing margin of the recovered clock in the RX. This THBR adaptive RX is fabricated in TSMC 28-nm CMOS technology with a core area of 0.097 mm2. The measured bit error rate (BER) is less than 10-12 for a 36-Gb/s pseudorandom binary sequence (PRBS) of 27 - 1, when the channel loss is 19 dB at 18 GHz. The total power consumption of this RX is 76 mW with gated adaptation circuits. The calculated figure of merit (FoM) is 2.1 pJ/bit. © 1993-2012 IEEE.

关键词： Energy efficiency

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A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2024年第8期32卷 1512-1522页

作者： Lin, Jhe-En Lan, Yi-Hao Liu, Shen-Iuan National Taiwan University Graduate Institute of Electronics Engineering The Department of Electrical Engineering Taipei10617 Taiwan

This article presents a 40-Gb/s (25.6 GBaud) quarter-rate receiver utilizing three-level pulse amplitude modulation (PAM). The continuous-time linear equalizer (CTLE) with a passive high-pass filter provides a boosting gain of 13 dB at 12.8 GHz. A two-tap data decision feedback equalizer (DFE) and a one-tap edge DFE are included. The phase detector (PD) logic directly controls the digitally controlled oscillator (DCO) to reduce the loop latency. This receiver is fabricated by a 28-nm CMOS process and its area is 0.12 mm2. By using a pseudorandom ternary sequence (PRTS) of 37 - 1 , this 40-Gb/s receiver compensates the channel loss up to 23-dB loss with a bit error rate (BER) -12. The total power consumption of this receiver is 90 mW at 40-Gb/s, which achieves an FoM of 98 fJ/bit/dB. © 1993-2012 IEEE.

关键词： Pulse amplitude modulation

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A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2024年第10期32卷 1878-1888页

作者： Lin, Yu-Cheng Chiou, Ren-Hao Yang, Chia-Hsiang National Taiwan University Graduate Institute of Electronics Engineering Taipei106 Taiwan Synopsys Hsinchu300 Taiwan National Taiwan University Department of Electrical Engineering Graduate Institute of Electronics Engineering Taipei106 Taiwan

In a multiuser multiple-input multiple-output (MU-MIMO) downlink system, users are susceptible to interuser interference (IUI) because of data being simultaneously transmitted over the same time-frequency resources. Conventionally, precoding algorithms aim to eliminate the IUI. However, constructive interference (CI) precoding can achieve better error performance by exploiting the IUI. This article presents a high-throughput CI precoder. Design optimization across the algorithm and the architecture layers is conducted, reducing the complexity for multiplications by 81.6%. As the number of iterations for convergence varies, dynamic resource allocation is utilized to support each modulation mode with maximized utilization: time-multiplexing for the 4-QAM mode and parallel-processing for the 16-QAM mode. The proposed symbol updater also allows more efficient scheduling. As a proof of concept, a CI precoder chip that supports up to 16 × MU-MIMO systems is designed based in a 40-nm CMOS technology. The performance gains at a bit error rate (BER) = 10-4 are 10.7 and 12.5 dB for 4-QAM and 16-QAM, respectively, compared with conventional regularized zero-forcing (RZF) schemes. The precoder delivers a maximum throughput of 3.2 Gb/s at a clock frequency of 200 MHz for the 16 × MU-MIMO configuration. © 1993-2012 IEEE.

关键词： Bit error rate

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A 73.8k-Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition

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IEEE Journal of Solid-State Circuits 2024年第10期59卷 3357-3365页

作者： Tong, Tzu-Wei Chen, Tai-Jung Hsieh, Yi-Yen Yang, Chia-Hsiang National Taiwan University Graduate Institute of Electronics Engineering Taipei10607 Taiwan MediaTek Hsinchu30078 Taiwan National Taiwan University Department of Electrical Engineering The Graduate Institute of Electronics Engineering Taipei10607 Taiwan

Machine learning (ML) has been widely adopted in neural signal processing and support vector machine (SVM) stands out for its efficacy given limited training data. The constrained battery capacity of implanted devices necessitates a dedicated accelerator with high energy efficiency. This work presents an energy-efficient SVM learning accelerator for brain pattern recognition. By employing the cluster-partitioning SVM (CP-SVM) algorithm, this work achieves up to 99% and 91% latency reductions for training and inference, respectively, compared to the conventional SVMs. Efficient hardware mapping is achieved through algorithm and architecture co-optimizations. Kernel transformation reduces the processing element (PE) array's hardware complexity by 42%. Sparsity-aware skipping eliminates redundant computations, leading to latency reduction. The design space of the PE array is explored to minimize the hardware cost. Data scheduling is applied to improve the PE utilization. Overall, the processing latency for the PE array is reduced by 96%. For PE array implementation, the area of the data exchanger is reduced by 93% by utilizing the chained interconnect. By integrating multiple sorters into one cross-cluster sorter, the sorter area is reduced by 52%. Fabricated in a 40-nm CMOS technology, the proposed SVM learning processor dissipates 9.68 mW at 40 MHz from a supply voltage of 0.85 V. The chip achieves the energy efficiency of 73.8k inference/mJ and 811 training/mJ, exceling prior arts by over 3.4× and 6.9×, respectively. It also delivers the area efficiency of 510k inference/s/mm2 and 5.6k training/s/mm2, outperforming the state-of-the-art by over 19.3× and 40.9×, respectively. © 2024 IEEE.

关键词： Clustering algorithms

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