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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Chuang, Je-Wei Wu, Zong-Han Huang, Bo-Ying Chang, Yao-Wen Graduate Institute of Electronics Engineering National Taiwan University Taipei106319 Taiwan Department of Electrical Engineering National Taiwan University Taipei106319 Taiwan

ISBN: (纸本)9798400706011

In modern advanced packaging, redistribution layers (RDLs) are often used for signal transmission among chips, and vias are used for communication among different layers. Most existing RDL routers perform via planning before routing. However, since vias can be placed at arbitrary locations under the irregular via structure, via planning limits the solution space and reduces layout flexibility. This paper proposes a new flow with a novel routing graph model for 90- and 135-degree routing, which allows dynamic via insertion during routing. The proposed algorithm enlarges the solution space by providing more choices during path-finding, achieving higher routing quality. The experimental results based on commonly used benchmark suites show that our router achieves over 10% better wirelength with over 29X speedup over the state-of-the-art work and even achieves 0.4% better wirelength with 55X speedup over the state-of-the-art any-angle router. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Dynamic routing algorithms

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Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards 24

Late Breaking Results: Power Rail Routing for Advanced Multi...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Tseng, Wei-Che Cai, Zong-Ying Huang, Yi-Ping Lo, Yu-Hsiang Chang, Yao-Wen Graduate Institute of Electronics Engineering National Taiwan University Taipei106319 Taiwan Department of Electrical Engineering National Taiwan University Taipei106319 Taiwan

ISBN: (纸本)9798400706011

This paper proposes a power rail routing flow for advanced multi-layered printed circuit boards (PCBs) to optimize segment area and via usage while satisfying IR drop requirements. With increasing current/voltage demands in modern PCBs, ultra-wide power rails may consume most routing space and cause significant routing problems. We present an effective overlap-aware rail sizing technique to distribute routing spaces appropriately according to current/voltage demands and a resistance-aware A∗-search algorithm to resolve overlapping regions by rail detouring. Experimental results show that our work significantly outperforms the state-of-the-art rail router in the metal area and runtime, achieving respective reductions of 49% and 28%, without any current/voltage violations. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Printed circuit boards

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Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes 24

Mixed-Size 3D Analytical Placement with Heterogeneous Techno...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Chen, Yan-Jen Hsieh, Cheng-Hsiu Su, Po-Han Chen, Shao-Hsiang Chang, Yao-Wen Graduate Institute of Electronics Engineering National Taiwan University Taipei106319 Taiwan Department of Electrical Engineering National Taiwan University Taipei106319 Taiwan

ISBN: (纸本)9798400706011

This paper proposes a mixed-size 3D analytical placement framework for face-to-face stacked integrated circuits fabricated with heterogeneous technology nodes and connected by hybrid bonding technology. The proposed framework efficiently partitions a given netlist into two dies and optimizes the positions of each macro, standard cell, and hybrid bonding terminal (HBT). A multi-technology objective function and a multi-technology density penalty calculation process are adopted to handle the heterogeneous-technology-node constraints during mixed-size 3D global placement. Furthermore, a 3D objective function is used to refine the placement result during HBT-cell co-optimization. Our placer achieves the best results for all contest test cases compared with the participating teams at the 2023 CAD Contest at ICCAD on 3D Placement with Macros. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Hybrid integrated circuits

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Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints 24

Late Breaking Results: Modern Automatic PCB Placement with C...

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61st ACM/IEEE Design Automation Conference, DAC 2024

作者： Tsou, Chien-Hao Lin, Sheng-Yah Hung, Wei-Chen Chang, Yao-Wen Graduate Institute of Electronics Engineering National Taiwan University Taipei106319 Taiwan Department of Electrical Engineering National Taiwan University Taipei106319 Taiwan

ISBN: (纸本)9798400706011

Existing printed circuit board (PCB) placement often fails to address complex constraints (e.g., diverse wire widths and intricate spacing rules) arising from heterogeneous components in modern designs. Manual placement requires expertise and is time-consuming. Thus, automated PCB placement is desired for large-scale, complex designs considering irregular component shapes, clearance conditions, wire areas, power circuit flow, and routability. This paper proposes an efficient force-directed global placement followed by legalization to handle these constraints. We derive power circuit anchor points to guide global placement when considering the power circuit flow and present a simulated annealing-based pad alignment method to handle complex spacing constraints. After global placement, we perform window-based legalization to remove component overlaps considering various constraints. Experimental results show our placer's superior routability and efficiency with complex constraints. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Simulated annealing

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Time-Switching Symmetric Transmitter Array to Increase Sweet Region for Far-Field Wireless Power Transmission Under Receiver Rotation and Location Variation

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IEEE Transactions on Microwave Theory and Techniques 2023年第2期71卷 881-897页

作者： Lu, Hsin-Chia Lu, Ling-Zhu Cai, Yu-Heng Tseng, Ching-Ya Graduate Institute of Electronics Engineering National Taiwan University Department of Electrical Engineering Taipei10617 Taiwan Graduate Institute of Communication Engineering National Taiwan University Taipei10617 Taiwan Tsmc Hsinchu300-096 Taiwan RealTek Inc. Hsinchu300 Taiwan

For wireless power transfer using linear-polarized transmitter (TX) and receiver antennas, the rotation and movement of receiving antenna cause received power variation. The received power pattern is proposed to describe the received power variation from a specific TX antenna under receiver rotation. By placing the peak of the received power pattern of additional TX antennas in null directions of the previous TX antenna, received power variation due to rotation can be compensated. With symmetrically placed TX antennas, the power variation due to location variation can be compensated. This article proposes a time-switching symmetric transmitting array combining both techniques to increase the sweet region for far-field wireless power transfer under rotation and location variation. A sweet region is an area in the 2-D case or volume in the 3-D case, which is defined as an area or a volume inside the TX array that can get guaranteed minimum received power under rotation. The received power calculation using the Friis equation with short dipole antenna pattern shows that a symmetric TX array can achieve a larger sweet region than an asymmetric TX array under the same total transmitted power. The efficiency for the receiver at the origin is 1/2 at the 2-D case and 1/3 at the 3-D case. In the experiment, a linear-polarized TX array at 915 MHz with monopole receiver antenna and power detector is used as the receiver to measure received power under rotation and location variation. Measurement results at 2-D and 3-D cases confirm the received power level predicted by calculation using the Friis equation. The power budget calculation for wirelessly powering a sensor module attached on a bee inside a beehive using the proposed 3-D TX array shows that it is feasible to deliver sufficient power to the sensor module regardless of the orientation and location of the bee inside the beehive. © 1963-2012 IEEE.

关键词： Dipole antennas

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Feature Selection Improves Speech Based Parkinson’s Disease Detection Performance

Feature Selection Improves Speech Based Parkinson’s Disease...

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17th International Joint Conference on Biomedical engineering Systems and Technologies, BIOSTEC 2024

作者： Tekindor, Ayşe Nur Aydın, Eda Akman Electrical and Electronics Engineering Graduate School of Natural and Applied Sciences Gazi University Ankara Turkey Department of Electrical and Electronics Engineering Faculty of Technology Gazi University Ankara Turkey

Parkinson’s disease (PD) is a neurodegenerative disorder that is caused by decrease in dopamine levels in the brain. There is currently no cure for PD;however, the progression of the disease can be brought under control by diagnosis made in early stages. Studies have shown that speech impairments are early symptoms of PD. In this study, an approach for the early diagnosis of patients with PD using speech based features was proposed. In order to detect the PD, four feature groups such as Bark Spectrum coefficients, Mel Frequency Cepstral Coefficients (MFCCs), Gammatone Cepstral Coefficients (GTCCs), and Spectral-Temporal Features were created. Minimum Redundancy Maximum Relevance (mRMR) based feature selection was applied to each feature group. Three classifiers including decision tree, Naive Bayes, and support vector machine were employed to evaluate the performance of the feature sets. The proposed method was validated on the Italian speech dataset. Feature selection improved the PD diagnosing performance, especially for the Naive Bayes model which obtained 96.01% accuracy by overall feature selection and 96.17% by group-based feature selection. © 2024 by Paper published under CC license (CC BY-NC-ND 4.0).

关键词： Neurodegenerative diseases

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Subtractive Microfluidics in CMOS

Subtractive Microfluidics in CMOS

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2024 IEEE International Electron Devices Meeting, IEDM 2024

作者： Weng, Wei-Yang Di, Alexander Zhang, Xiang Tsai, Ya-Chen Hsiao, Yan-Ting Chien, Jun-Chau Department of Electrical Engineering and Computer Sciences University of California Berkeley United States Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9798350365429

This paper introduces a microfluidics platform embedded within a silicon chip implemented in CMOS technology. The platform utilizes a one-step wet etching method to create fluidic channels by selectively removing CMOS back-end-of-line (BEOL) routing metals. We term our technique "subtractive" microfluidics, to complement those fabricated with additive manufacturing. Three types of structures are presented in a TSMC 180-nm CMOS chip: (1) passive microfluidics in the form of a micro-mixer and a 1:64 splitter, (2) fluidic channels with embedded ion-sensitive field-effect transistors (ISFETs) and Hall sensors, and (3) integrated on-chip impedance-sensing readout circuits including voltage drivers and a fully differential transimpedance amplifier (TIA). Sensors and transistors are functional pre- and post-etching with minimal changes in performance. Our CMOS subtractive microfluidics technique enables tight integration of fluidics and electronics, paving the way for future small-size, high-throughput lab-on-chip (LOC) devices. © 2024 IEEE.

关键词： CMOS integrated circuits

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Sub-optimal Perceptron Controller Using WOA Algorithm for Farming Watering Mobile Robot

Sub-optimal Perceptron Controller Using WOA Algorithm for Fa...

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2024 IEEE Latin American Conference on Computational Intelligence, LA-CCI 2024

作者： Pastrana, M.A. Oliveira, L.H. Bautista, J. Pinto-Lopera, Jesus Mendoza-Penaloza, Jose Munoz, Daniel M. University of the Amazonia Faculty of Engineering Systems Undergraduate Program Florencia Caquetá Colombia University of Brasilia Mechatronics Graduate Program Department of Mechanical Engineering Brasilia Brazil University of Brasilia Faculty of Gama Electronics Engineering Undergraduate Program Brasilia Brazil

ISBN: (纸本)9798350374575

Artificial neural networks (ANNs) are intricate mathematical models, drawing inspiration from the biological nervous system, and offering intelligence alongside nonparametric capabilities. The efficacy of ANNs heavily relies on their learning process. Heuristic search algorithms have been proposed in literature as reliable options for optimizing neural networks utilizing the Perceptron architecture. This paper presents an suboptimal neural network Perceptron training method employing the Whale Optimization Algorithm for the application of farming watering mobile robots. To achieve this, a fitness function based on system responses such as overshoot, settling Time, and steady-state Error was developed. The sub-optimal Perceptron controller was then implemented using MATLAB, CoppeliaSim software and the EVA robot, resulting in a 66.17% overshoot, a 4.7% steady-state error, and a settling time of 3.05 seconds. Moreover, the sub-optimal Perceptron controller was mapped onto a System on Chip FPGA AMD-Xilinx Zynq 7020, resulting in a hardware resources consumption of 1,870 (3.52%) Lookup table, 2 (0.9%) Digital Signal Processing blocks, 1,019 (0.96%) Flip-Flops and a power consumtion of 0.005 W. Finally, Hardware-in-The-Loop validation was performed using CoppeliaSim, Python, Universal Direct Memory Access, and the EVA robot. The results showed an overshoot of 94.83%, a settling time of 2 seconds, and a steady-state error of 4.5%. © 2024 IEEE.

关键词： MATLAB

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Bringing Bearing Fault Detection to Embedded Systems Using Low-Cost Machine Learning Techniques

Bringing Bearing Fault Detection to Embedded Systems Using L...

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2024 IEEE Latin American Conference on Computational Intelligence, LA-CCI 2024

作者： Teixeira, Natalia S. Pastrana, M.A. Moura, Henrique G. Munoz, Daniel M. University of Brasilia Faculty of Gama Automotive Engineering Undergraduate Program Brasilia Brazil University of Brasilia Department of Mechanical Engineering Mechatronics Graduate Program Brasilia Brazil University of Brasilia Faculty of Gama Electronics Engineering Undergraduate Program Brasilia Brazil

ISBN: (纸本)9798350374575

Vibration analysis is crucial for predictive maintenance of bearing systems, aiming to reduce costs and prevent failures. This paper investigates signal processing techniques such as FFTs and Hilbert Transforms for fault diagnosis, alongside decision tree models, particularly the J48 algorithm within the WEKA environment, for fault classification. The study emphasizes the integration of signal processing and machine learning for effective fault diagnosis and maintenance. Notably, a classification model with low computational cost has been chosen, facilitating implementation in embedded systems. This model also offers interpretability of outputs, as it is based on decision trees of frequency components obtained through preprocessing. © 2024 IEEE.

关键词： Predictive maintenance

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3D SRAM Using Ultrathin Body Nanosheets and Bitline Signal Decoupling

IEEE Electron Device Letters

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IEEE Electron Device Letters 2023年第12期44卷 1975-1978页

作者： Chou, Tao Wang, Li-Kai Chung, Tsai-Yu Yao, Ching-Wang Lin, Hsin-Cheng Liu, C.W. National Taiwan University Graduate School of Advanced Technology Taipei10617 Taiwan Graduate Institute of Photonics and Optoelectronics National Taiwan University Taipei10617 Taiwan Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan Graduate Institute of Electronics Engineering The Graduate Institute of Photonics and Optoelectronics The Graduate School of Advanced Technology National Taiwan University Department of Electrical Engineering Taipei10617 Taiwan

The heterogeneous vertically stacked 4T/2T SRAM is optimized using buried power rails and buried signal rails. The bitcell area of 3D SRAM can be reduced by 28% compared to 6T SRAM without transistor stacking. SRAM performance is improved by increasing nanosheet nFET floor numbers without minimum operating voltage degradation. Ultrathin bodies can reduce parasitic capacitance thanks to the total gate metal height reduction. Bitline signal decoupling can reduce read time by 12%. 166ps read time and 65ps write time can be achieved with 5nm of body thickness, 25nm of nanosheet width, and floor number = 5. With 3nm of body thickness, read and write time are further reduced by 5% and 8%, respectively, even with 13% low-field mobility degradation. © 1980-2012 IEEE.

关键词： Nanosheets

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