检索结果-内蒙古大学图书馆

2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024

作者： Kuo, Li-An Huang, Jiun-Lang Graduate Institute of Electronics Engineering Department of Electrical Engineering Taiwan Graduate Institute of Communication Engineering Department of Electrical Engineering Taiwan National Taiwan University Department of Electrical Engineering Taiwan

ISBN: (纸本)9798350360349

Software-based self-testing is a promising solution to post-deployment testing for processor cores embedded in long-life mission-critical systems. One popular approach to self-test program generation is to convert each scan-based test pattern to an instruction sequence that, when executed, implicitly applies the test pattern. However, this approach suffers low conversion quality for branch instructions. In this paper, we develop a branch-aware test program generator to improve the conversion efficiency for branch instructions. The test program generator considers the actual and predicted branch conditions to derive the instruction addresses that guarantee the desired program execution order. Furthermore, we optimize the test program template and recycle the wasted program blocks to reduce the test program footprint. The proposed test program generator is applied to a five-stage RISC-V processor with branch prediction. The generated test program achieves 90.68% transition delay fault coverage and reduces the test program size by 76%. © 2024 IEEE.

关键词： Software testing

来源：评论

学校读者我要写书评

暂无评论

Online learning of stable robust adaptive controllers design based on data-dependent feedback linearization with application to rotary inverted pendulum

引用

Neural Computing and Applications 2024年第18期36卷 10881-10896页

作者： Soydemir, Mehmet Uğur Şahin, Savaş Kocaoğlu, Aykut Bulucu, Parvin Güzeliş, Cüneyt Department of Electrical and Electronics Engineering İzmir Katip Çelebi University İzmir Turkey Department of Electrical and Energy İzmir Vocational School Dokuz Eylül University İzmir Turkey Department of Electrical and Electronics Engineering Graduate School Yaşar University İzmir Turkey Department of Electrical and Electronics Engineering Yaşar University İzmir Turkey

This study introduces an online (supervised) learning method to design nonlinear auto-regressive moving average (NARMA) controllers for feedback-linearized nonlinear single-input single-output (SISO) systems. The algorithm ensures Schur stability of the overall closed-loop system and provides adaptiveness and robustness for the NARMA controllers. The first stage of the method derives, in a data-dependent way, a feedback-linearized model of the nonlinear plant by using its input and output sample pairs. The method’s second stage, which constitutes the novel part of the presented study, builds up an online learning scheme for the linear auto-regressive moving average (ARMA) controller based on an already learned feedback-linearized model of the nonlinear plant. During online supervised learning, ARMA parameters of the feedback-linearized SISO plant model and the closed-loop ARMA model are computed by minimizing the plant identification and the closed-loop system tracking errors. Both errors are defined as 1,Ε, namely Ε-insensitive loss functions that provide NARMA controller the robustness against noise and outliers. The proposed online learning control algorithm is applied to a rotary inverted pendulum model and to a real rotary inverted pendulum setup. The tracking performance of the developed controller is compared with those of the linear quadratic regulator and coupled sliding mode controller in terms of mean square error. © The Author(s) 2024.

关键词： Feedback linearization

来源：评论

学校读者我要写书评

暂无评论

Reduced-RSS: Reduced Residual Search Space for Nash Bargaining Solutions

引用

IEEE Transactions on Vehicular Technology 2025年第5期74卷 8215-8225页

作者： Cha, Chaeyeon Park, Hyunggon Ewha Womans University Graduate Program in Smart Factory Department of Electronic and Electrical Engineering Seoul03760 Korea Republic of

A fair and efficient resource allocation is crucial to maximize the efficiency of vehicular networks with time-varying resources among dynamically changing vehicles. The Nash Bargaining Solution (NBS) from the cooperative game theory has been one of the fair and optimal resource management solutions for multiple users. However, the computational complexity required to find the NBS for general utility functions exponentially increases either as the number of users increases or as the resources change over time. This is because the size of bargaining sets where the NBS should be found changes. In this paper, we propose an algorithm to reduce the size of the search spaces by considering the adjacent bargaining sets correlated by resource changes. We use the axiom of independence of linear transformations in NBS for the linear approximation of NBS in the adjacent bargaining sets based on its linear transform, leading to reduced residual search space. Moreover, we prove that the NBS is always included in the reduced residual search space based on the axiom of independence of irrelevant alternatives in NBS. Through simulations and experiments on synthetic and real traffic data, we demonstrate that the complexity of existing algorithms for NBS is lowered with the reduced residual search spaces. © 1967-2012 IEEE.

关键词： NIST Resource management Heuristic algorithms Vectors Dynamical systems Computational complexity Accuracy Vehicle dynamics Dynamic scheduling System performance

来源：评论

学校读者我要写书评

暂无评论

A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring

引用

IEEE Journal of Solid-State Circuits 2024年第6期59卷 1899-1911页

作者： Chen, Po-Shao Chen, Yen-Lung Lee, Yu-Chi Fu, Zih-Sing Yang, Chia-Hsiang Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan University of Michigan Department of Electrical Engineering and Computer Science Ann ArborMI48109 United States Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science CambridgeMA02139 United States National Taiwan University Department of Electrical Engineering Graduate Institute of Electronics Engineering Taipei10617 Taiwan

This work presents an accelerator that performs blind deblurring based on the dark channel prior. The alternating minimization algorithm is leveraged for latent image and blur kernel estimation. A 2-D Laplace equation solver is embedded to reduce the latency by 56% for boundary wrapping. For latent image estimation, gradient data locality is employed to reduce the latency by 57%. A sorting engine is designed to reduce the latency in data access by 96% for calculating the dark channel. A pipelined mixed-radix 1-D fast Fourier transform (FFT) engine is used for efficient latent image estimation and blur kernel estimation. By employing image size approximation, 85% of additions and 97% of multiplications for FFT can further be saved. In the blur kernel estimator, a 2-D convolution engine with a parallel architecture is implemented, reducing the latency by 79%. The accelerator supports blur kernels of 25times 25 and 49times 49 pixels for blurred images of 129times 129 and 257times 257 pixels, respectively. Fabricated in 40-nm CMOS, the accelerator's core area is 3.98 mm2. The chip dissipates 28.8 mW at 65 MHz from a 0.65-V supply. It can estimate a blur kernel of 25times 25 pixels for an image patch with 129times 129 pixels for deblurring a full-HD image in 1.7 s, achieving a 2562times shorter latency than a high-end CPU. Compared with the state-of-the-art design, the chip achieves a four times higher normalized area efficiency and a 7.5times higher normalized energy efficiency. © 1966-2012 IEEE.

关键词： CMOS integrated circuits

来源：评论

学校读者我要写书评

暂无评论

A 16-Gb/s Baud-Rate CDR Circuit with One-Tap Speculative DFE and Wide Frequency Capture Range

引用

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2024年第3期32卷 480-484页

作者： Chou, Po-Yuan Chen, Wei-Ming Liu, Shen-Iuan National Taiwan University Graduate Institute of Electronics Engineering Department of Electrical Engineering Taipei10617 Taiwan

A 16-Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap decision-feedback equalizer (DFE) and a wide frequency capture range (FCR) is presented. The proposed asymmetrical pattern-based phase detectors are used to achieve a wide FCR. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and the active area is 0.1094 mm2. For a 16 Gb/s PRBS of 27-1, the power of the CDR circuit is 38.4 mW and its calculated energy efficiency is 2.4 pJ/b. The measured FCR is 40.6%. © 1993-2012 IEEE.

关键词： Energy efficiency

来源：评论

学校读者我要写书评

暂无评论

Current Polarity Changeable Concentric MIS Tunnel Photodiode with Linear Photodetectivity via Inner Gate Biasing and Outer Ring Short-Circuit Operation

引用

IEEE Transactions on Electron Devices 2023年第10期70卷 5184-5189页

作者： Lin, Yu-Cin Hwu, Jenn-Gwo National Taiwan University Graduate Institute of Electronics Engineering Taipei10617 Taiwan National Taiwan University Graduate Institute of Electronics Engineering and the Department of Electrical Engineering Taipei10617 Taiwan

The coupling effect between neighbor electrodes in the concentric metal-insulator-semiconductor(p) tunnel diode (MIS(p) TD) was investigated. In the accumulation region, the diffusion current, resulting from the gradient of the electron concentration, is the dominant factor in the coupling effect. However, in the deep depletion region, the fringing field dominates. Based on the coupling mechanism, we propose a novel sensing method that measures the short-circuit current of the outer ring with the inner gate biasing. When the light intensity exceeds 100 lux, the short-circuit current increases linearly and switches from negative to positive at a specific threshold of light intensity, providing a significant advantage in photodetection. Moreover, the threshold is tunable by gate bias, and the linearity of the sensor ensures its accuracy and convenience. Additionally, biasing the outer ring to 0 V reduces power consumption. © 1963-2012 IEEE.

关键词： Photodetectors

来源：评论

学校读者我要写书评

暂无评论

Compact Model Build Upon Dynamic Weighting Artificial Neural Network Approach for Complementary Field Effect Transistors

引用

IEEE Transactions on Electron Devices 2024年第1期71卷 246-253页

作者： Butola, Rajat Li, Yiming Kola, Sekhar Reddy National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation The Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program The Institute of Communications Engineering the Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

In this work, a dynamic weighting-artificial neural network (DW-ANN) methodology is presented for quick and automated compact model (CM) generation. It takes advantage of both TCAD simulations for high accuracy and SPICE simulations for cost-effectiveness. This methodology is developed for gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field effect transistor (CFET), a potential candidate for future CMOS technology due to its innate properties. The critical process variation (PV) sources that severely degrade the CFET performance are estimated using DW-ANN. It reduces the computation cost and predicts the effects of PV sources with less than 1% error. Furthermore, a compact DW-ANN-based Verilog-A model has been developed that captures the dc as well as transient behavior accurately for circuit-level analysis. CFET-based circuits such as inverter, 6T-static random access memory (SRAM), and ring oscillator (RO) are characterized and implemented using DW-ANN-based CM. The overall average error of the model is reported as less than 2%. Therefore, the proposed device and circuit modeling approach provides a feasible solution for the rapid compact modeling of new emerging devices with good convergence and high accuracy. © 1963-2012 IEEE.

关键词： Neural networks

来源：评论

学校读者我要写书评

暂无评论

Relay-Assisted Carrier Aggregation (RACA) Uplink System for Enhancing Data Rate of Extended Reality (XR)

引用

IEEE Transactions on Vehicular Technology 2024年第5期74卷 7637-7650页

作者： Chen, Chi-Wei Tsai, Wen-Chiao Tsai, Lung-Sheng Wu, An-Yeu National Taiwan University Graduate Institute of Electronics Engineering Department of Electrical Engineering Taipei10617 Taiwan MediaTek Inc. Hsinchu30078 Taiwan

In Extended Reality (XR) applications, high data rates and low latency are crucial for immersive experiences. Uplink transmission in XR is challenging due to the limited antennas and power of lightweight XR devices. To improve data transmission rates, we investigate a relay-assisted carrier aggregation (RACA) system. The XR device simultaneously transmits data to an access point (AP) and a relay in proximity over low-frequency and high-frequency bands, respectively. Then, the relay down-converts and amplifies the signals to the AP, effectively acting as an additional transmit antenna for the XR device. In this paper, we propose two algorithms to maximize the data rate of the XR device in their respective protocols. In the centralized protocol, the rate maximization problem is equivalently transformed as a weighted mean square error minimization (WMMSE) problem which can be solved iteratively by alternative optimization. In the distributed protocol, the rate maximization problem is decomposed into two independent subproblems where the rate of the direct link and the rate of the relay link are maximized by singular value decomposition (SVD)- based methods with water-filling (WF). Simulation results show that the rate of the RACA system is improved by 32% compared to that of the conventional carrier aggregation scheme. © 1967-2012 IEEE.

关键词： Mean square error

来源：评论

学校读者我要写书评

暂无评论

Adjustable polymer dispersed liquid crystal grating

Adjustable polymer dispersed liquid crystal grating

引用

CLEO: Science and Innovations in CLEO 2024, CLEO: S and I 2024 - Part of Conference on Lasers and Electro-Optics

作者： Huang, Hsuan-Han Li, Yu-Jen Huang, Chiu-Chang Kuan, Chieh-Hsiung Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taiwan Graduate Institute of Biomedical Electronics and Bioinformatics Department of Electrical Engineering National Taiwan University Taiwan

The double-period grating structure is integrated in a polymer dispersed liquid crystal (PDLC) device and guides the arrangement of PDLC droplets. The grating period is changed by electronic control. © Optica Pub... 详细信息

关键词： Liquid crystals

来源：评论

学校读者我要写书评

暂无评论

Interfacial-Layer-Free Ge0.95Si0.05Nanosheet FeFETs

引用

IEEE Transactions on Electron Devices 2024年第3期71卷 1758-1763页

作者： Hsieh, Wan-Hsuan Chen, Yu-Rui Liu, Yi-Chun Zhao, Zefu Lee, Jia-Yang Tu, Chien-Te Huang, Bo-Wei Wang, Jer-Fu Lee, M.H. Liu, C.W. Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan Institute and Undergraduate Program of Electro-Optical Engineering Graduate School of Advance Technology National Taiwan University Taipei10617 Taiwan National Taiwan University Graduate School of Advance Technology Taipei10617 Taiwan Graduate Institute of Electronics Engineering Graduate Institute of Photonics and Optoelectronics Graduate School of Advanced Technology National Taiwan University Department of Electrical Engineering Taipei10617 Taiwan

The substantial memory window (MW) of 1.8 V is achieved by utilizing stacked two nanosheet (NS) gate-all-around (GAA) Ge0.95 Si0.05 ferroelectric field-effect transistors (FeFETs), employing a low write voltage of 2 V. The channel phosphorus concentration 1E18 cm-3 is used to erase the absence of interfacial layer (IL) can reduce the operation voltage. An isotropic wet etching process is employed for channel release. The stacked two NSs offer the advantages of reducing cell-to-cell variation and doubling the read current. Additionally, the stability of data storage is demonstrated with the data retention of >1E4 s, linearly extrapolated to a span of 10 years, and exhibiting high endurance >1E11 cycles. The thermal budget is as low as 400 °C. © 1963-2012 IEEE.

关键词： III-V semiconductors

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：