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2024 Conference on Lasers and Electro-Optics, CLEO 2024

作者： Huang, Hsuan-Han Li, Yu-Jen Huang, Chiu-Chang Kuan, Chieh-Hsiung Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taiwan Graduate Institute of Biomedical Electronics and Bioinformatics Department of Electrical Engineering National Taiwan University Taiwan

The double-period grating structure is integrated in a polymer dispersed liquid crystal (PDLC) device and guides the arrangement of PDLC droplets. The grating period is changed by electronic control. CLEO 2024 © ... 详细信息

ISBN: (纸本)9781957171395

关键词： Electrooptical effects

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Monolithic 3-D Self-Aligned Heterogeneous Nanosheet Channel Complementary FETs With Matched VT by Band Alignments of Individual Channels

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IEEE Transactions on Electron Devices 2024年第5期71卷 3383-3389页

作者： Hsieh, Wan-Hsuan Tu, Chien-Te Chen, Yu-Rui Huang, Bo-Wei Chen, Wei-Jen Liu, Yi-Chun Cheng, Chun-Yi Chou, Hung-Chun Liu, C.W. Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan National Taiwan University Graduate School of Advanced Technology Taipei10617 Taiwan National Taiwan University Department of Electrical Engineering Graduate Institute of Electronics Engineering Graduate Institute of Photonics and Optoelectronics Graduate School of Advanced Technology Taipei10617 Taiwan

Monolithic 3-D stacked Ge0.9Sn0.1 nanosheet and Ge0.75Si0.25 nanosheet complementary FETs with multiple P/N junction isolation by in-situ doped CVD epitaxy are experimentally demonstrated. Heterogeneous channels with common single work function metal (WFM) gate structure are fabricated as a CMOS inverter with the matched {V}-{text {T}} and good voltage transfer characteristics (VTCs). {V}-{text {T}} tuning is achieved individually by the band alignment of GeSi and GeSn for n-channel and p-channel, respectively, for the first time. The Hf0.2Zr0.8O2 gate stacks with extremely high boldsymbol {kappa } of 47 are integrated to enhance the {I}-{text {ON}} of complementary FET (CFET) for high performance. The monolithic stacked heterogeneous CFETs without the need of wafer bonding, dielectric isolation, selective epitaxial growth, and dual WFM can simplify the process for transistor 3-D stacking. © 1963-2012 IEEE.

关键词： Chemical vapor deposition

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Correntropy-Based Data Selective Adaptive Filtering

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IEEE Transactions on Circuits and Systems I: Regular Papers 2024年第2期71卷 754-766页

作者： Chien, Ying-Ren Wu, Sheng-Teng Tsao, Hen-Wai Diniz, Paulo S.R. Adaptive and Autonomous Communication Laboratory Department of Electrical Engineering National Ilan University Yilan City260007 Taiwan College of Electrical Engineering and Computer Science Graduate Institute of Communication Engineering National Taiwan University Taipei10617 Taiwan Program of Electrical Engineering Department of Electronics and Computer Engineering COPPE/Poli Universidade Federal do Rio de Janeiro Rio de Janeiro68504 Brazil

Data selection can be used in conjunction with adaptive filtering algorithms to avoid unnecessary weight updating and thereby reduce computational overhead. This paper presents a novel correntropy-based data selection method as an alternative to conventional data selection mechanisms based on squared error values. We developed a variable correntropy sensing algorithm to maximize the instantaneous correntropy function for the Gaussian kernel function to mitigate the impact of impulse noise and other forms of noise that can be disregarded in data selection. The proposed data selection mechanism can be implemented with any adaptive filtering algorithm. In simulations, the proposed method (implemented with the least mean squared algorithm) outperformed comparable error-based data selection schemes in terms of hit rate and miss rate, and the resulting weight updating ratio was close to the expected weight updating ratio. © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

关键词： Adaptive filters

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A Hyperbolic Micromagnet for Multiple Spin Qubits with Fast Rabi Oscillations and High Addressability

IEEE Electron Device Letters

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IEEE Electron Device Letters 2024年第4期45卷 526-529页

作者： Chang, Che-Hao Li, Yu-Cheng Wu, Yu-Jui Liao, Chen-Yao Lin, Min-Jui Tsao, Hung-Yu Li, Jiun-Yun Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science CambridgeMA02139 United States National Taiwan University Department of Electrical Engineering Graduate Institute of Electronics Engineering Graduate School of Advanced Technology Taipei10617 Taiwan Taiwan Semiconductor Research Institute Hsinchu30078 Taiwan

We demonstrate a hyperbolic micromagnet to increase the manipulation speed of electron spins in silicon quantum dots using electric dipole spin resonance (EDSR). For single qubits, the hyperbolic magnet provides a large gradient of transverse magnetic fields of 4.9 mT/nm with the corresponding Rabi frequency ( 69 MHz). We then demonstrate that this hyperbolic micromagnet can drive a linear array of qubits with Rabi frequencies of 19 69 MHz and a high addressability (minimum difference of Larmor frequencies) up to 590 MHz to suppress the crosstalk between different qubits. We show that 15 qubits can be effectively addressed for high fidelity by this hyperbolic micromagnet. © 1980-2012 IEEE.

关键词： Magnetic fields

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A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation

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IEEE Journal of Solid-State Circuits 2023年第3期58卷 806-816页

作者： Kang, Zhi-Heng Liu, Shen-Iuan National Taiwan University Graduate Institute of Electronics Engineering The Department of Electrical Engineering Taipei10617 Taiwan

A digital phase-locked loop (DPLL) using the feedforward phase-error cancellation (FPC) is presented. The phase error of this DPLL using a digitally controlled ring oscillator is quickly canceled by a digitally controlled delay line (DCDL), which improves the phase noise performance. The loop gain of this FPC DPLL is also calibrated. In addition, a dead-zone-free (DZF) bang-bang phase-frequency detector (BBPFD) is presented to enhance the resolution of the time-to-digital converter (TDC). This proposed DPLL is fabricated in a 40-nm CMOS process which occupies 0.05 mm2. The measured rms jitter integrated from 1 kHz to 100 MHz is 788 fs at 1.6 GHz. The measured reference spur is -57.84 dBc for a 50 MHz reference frequency. Its power consumption is 5 mW for a 1.1-V supply voltage. © 1966-2012 IEEE.

关键词： Phase noise

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A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2023年第4期32卷 704-713页

作者： Lan, Yi-Hao Liu, Shen-Iuan The Graduate Institute of Electronics Engineering The Department of Electrical Engineering National Taiwan University Taipei10617 Taiwan

A 32-Gb/s 2× half-baud-rate (THBR) clock and data recovery (CDR) circuit is presented by using a phase detector (PD) and a frequency detector (FD). The frequency detection range of the FD is analyzed. This prototype is fabricated in a 28-nm CMOS process with an active area of 0.055 mm2. The measured frequency capture range is 43.7% for a 32-Gb/s pseudorandom bit sequence (PRBS) of 27-1. This proposed CDR circuit achieves a bit error rate of less than 10−12 under the channel loss of 23 dB at 16 GHz. The total power consumption is 58.6 mW at 32 Gb/s and achieves a figure-of-merit (FoM) of 0.079 pJ/bit/dB. © 2023 IEEE.

关键词： Energy efficiency

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A Hybrid Islanding Detection Technique using Voltage Positive Feedback and Frequency Deviation in GFM based Microgrid

A Hybrid Islanding Detection Technique using Voltage Positiv...

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2024 IEEE PES/IAS PowerAfrica, PowerAfrica 2024

作者： Diouf, Alioune Noro, Yasuhiro Electrical Engineering and Electronics Program Kogakuin University Tokyo Japan Kogakuin University Department of Electrical and Electronics Engineering Tokyo Japan

ISBN: (纸本)9798350389388

This paper introduces a grid forming(GFM) inverter equipped with a hybrid islanding detection method which combined the positive feedback(PF) of the point of common coupling(PCC) voltage based active method used and the frequency deviation as a passive method. The proposed algorithm is implemented inside the GFM voltage controller. Furthermore, a frequency deviation threshold is addressed based on a theoretical approach in order to relieve continuous disturbance injection. This hybrid method doesn't undergo a non-detection zone(NDZ) and, an additionally, a continuous operation of the microgrid is achieved. Moreover, the proposed algorithms can distinguish islanding phenomenon against load switching during grid connected mode. The results are evaluated by simulations using ATPdraw software. © 2024 IEEE.

关键词： autonomous operation distributed generators grid forming hybrid islanding detection islanding detection positive feedback

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A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality

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IEEE Journal of Solid-State Circuits 2024年第11期59卷 3840-3852页

作者： Huang, Wen-Cong Lin, I-Ting Lin, Ying-Sheng Chen, Wen-Ching Lin, Liang-Yi Chang, Nian-Shyang Lin, Chun-Pin Chen, Chi-Shi Yang, Chia-Hsiang National Taiwan University Graduate Institute of Electronics Engineering Taipei106216 Taiwan MediaTek Hsinchu300096 Taiwan University of California at Berkeley Department of Electrical Engineering and Computer Sciences BerkeleyCA94720 United States Taiwan Semiconductor Research Institute Hsinchu300091 Taiwan Graduate Institute of Electronics Engineering National Taiwan University Department of Electrical Engineering Taipei106216 Taiwan

Augmented reality (AR) has been applied to various mobile applications. Modern AR algorithms include neural networks, such as convolutional neural networks (CNNs) and graph convolutional networks (GCNs). The high computational complexity of these networks poses challenges for real-time operation on energy-constrained devices. This article presents the first energy-efficient hybrid CNN-GCN system-on-chip (SoC) for mobile AR. A CNN engine exploits the channel-wise structured feature sparsity to eliminate redundant computations and data movements. By utilizing the proposed channel-sparse encoding scheme on a specialized processing element (PE) architecture, up to 8× higher throughput and × higher energy efficiency can be achieved. A reconfigurable convolution PE (CPE) array is deployed for efficient CNN inference. A GCN engine is designed to implement skeleton-based action recognition and gesture recognition. Up to 71% of total operations and 39% of memory footprint can be reduced by leveraging the data and graph properties. A RISC-V MCU is integrated for system control and network deployment. The proposed SoC is implemented in a 28-nm CMOS technology with a core area of 8.28 mm2. By exploiting various sparsity levels across network layers, the chip achieves an up to 3.277-TOPS peak performance and a 25.1-TOPS/W energy efficiency for sparse CNN inference, 2.0× higher energy-efficient than prior arts. It also achieves an up to 72 actions/s recognition throughput, 18× faster than the state of the art. © 2024 IEEE.

关键词： Engines

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Breakdown Voltage Enhancement of Nanosheet Transistors by Ultrathin Bodies

IEEE Electron Device Letters

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IEEE Electron Device Letters 2024年第6期45卷 956-959页

作者： Huang, Bo-Wei Hsieh, Wan-Hsuan Tu, Chien-Te Liu, Yi-Chun Chen, Yu-Rui Chen, Wei-Jen Cheng, Chun-Yi Chou, Hung-Chun Liu, C.W. National Taiwan University Graduate Institute of Electronics Engineering Taipei106 Taiwan National Taiwan University Graduate School of Advanced Technology Taipei106 Taiwan Graduate Institute of Electronics Engineering The Graduate Institute of Photonics and Optoelectronics The Graduate School of Advanced Technology National Taiwan University Department of Electrical Engineering Taipei106 Taiwan

A high breakdown voltage of 11.7 V is achieved for a GeSn ultrathin (∼2 nm) body nanosheet p-channel field-effect transistor. This voltage is 5.7 V higher than that for a 10-nm GeSn nanosheet. The large effective bandgap associated with the quantum confinement in the ∼2-nm Ge0.9Sn0.1 channel is responsible for the enhanced breakdown voltage. An extremely scaled Ge0.9Sn0.1 ultrathin body with channel thickness reduced to ∼2 nm is realized through the co-optimization of low-temperature epitaxy and selective isotropic etching. As-grown Ge0.9Sn0.1 channel layers as thin as 4 nm sandwiched by Ge0.97Sn0.03/Ge caps are carefully designed for ultrathin bodies. Radical-based highly selective isotropic dry etching is adopted to etch the caps and sacrificial layers and to release the GeSn ultrathin body channels. In addition, owing to strong quantum confinement in the ∼2-nm ultrathin body, a high ION/IOFF ratio of ≥1.7 × 107 at VDS =-0.5 V is achieved. . © 1980-2012 IEEE.

关键词： Electric breakdown

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A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator

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IEEE Journal of Solid-State Circuits 2023年第2期58卷 520-529页

作者： Shen, Hsueh-Yen Lee, Yu-Chi Tong, Tzu-Wei Yang, Chia-Hsiang Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan MediaTek Hsinchu300 Taiwan Department of Electrical Engineering Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan

Super-resolution has been utilized in a plenty of applications to provide better visual experience. To meet the high-throughput and low-power needs, some dedicated accelerators for super-resolution have been proposed. Neural-network (NN)-based super-resolution accelerators achieve impressive restoration performance, but the high-computational complexity does not allow a high throughput for video streaming. This work presents a super-resolution accelerator that implements the rapid and accurate image super-resolution (RAISR) algorithm for reconstructing super-resolution images. The utilization of the low-resolution (LR) upscaler is increased by 50% by the proposed memory scheduling scheme. Kernel compression is utilized to reduce the overall on-chip memory by 72%. A patch reuse scheme achieves a 91% reduction in external memory access times compared to the direct-mapped design. The architecture is flexible to reconstruct full HD images with a variety of upscaling factors (2×, 3×, 4×). Fabricated in a 40-nm CMOS technology, the proposed super-resolution accelerator integrates 3.11-M gates in a core area of 3.33 mm2. The chip is able to deliver a throughput of 90 frame/s (fps) for all supported upscaling factors and dissipates 91 mW at 200 MHz. Compared with the state-of-the-art designs, this work achieves a 5.4-to-28.4× higher normalized throughput with 5.1-to-36× lower normalized energy dissipation. © 1966-2012 IEEE.

关键词： Image reconstruction

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